Method and Apparatus for MOSFET Drain-Source Leakage Reduction

• US 20090201075A1
• Filed: 03/06/2009
• Published: 08/13/2009
• Est. Priority Date: 02/12/2008
• Status: Abandoned Application

• Current Assignee: Semi Solutions LLC
• Original Assignee: Semi Solutions LLC
• Inventors: Tsividis, Yannis
• Application Number:
  US12/399,759
• Publication Number:
  US 20090201075A1
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A method and apparatus are taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS logic gate, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. The first transistor'"'"'s gate is controlled by a digital voltage source having a same polarity as that of an output of the CMOS logic gate and the second transistor is controlled by a digital voltage source having a same polarity as that of an input to the CMOS logic gate.

Claims

1. A leakage control circuit for a complementary metal-oxide semiconductor (CMOS) gate, comprising:

a CMOS logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal; and

a control circuit coupled to at least one of said first NMOS transistor and said first PMOS transistor, said control circuit comprising;

a first transistor coupled to said body terminal of any of said NMOS transistor and said PMOS transistor to bring said body terminal to a first reference potential; and

a second transistor coupled to said body terminal of any of said NMOS transistor and said PMOS transistor to bring said body terminal to a second reference potential, said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER);

wherein said first transistor'"'"'s gate is controlled by a digital voltage source having a same polarity as that of an output of said CMOS logic gate and said second transistor is controlled by a digital voltage source having a same polarity as that of an input to said CMOS logic gate.

2. The circuit of claim 1, wherein said CER expresses a ratio between a current of said drain of any of said NMOS transistor and said PMOS transistor with body bias to a current of said drain of any of said NMOS transistor and said PMOS transistor without body bias.

3. The circuit of claim 1, wherein said CER expresses a ratio of width over the length of a reference current device and width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

4. The circuit of claim 1, wherein the CMOS gate comprises any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.

5. The circuit of claim 1, further comprising:

a second CMOS logic gate, wherein the leakage control circuit controls the leakage of said second CMOS logic gate.

6. The circuit of claim 1, further comprising:

a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.

7. The circuit of claim 1, further comprising:

a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.

8. The circuit of claim 1, further comprising:

a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.

9. A circuit comprising:

a first MOS transistor having a gate terminal, a source terminal, a drain terminal, and a body terminal; and

a control circuit coupled to said MOS transistor, said control circuit comprising;

a second MOS transistor coupled to said body terminal of said first MOS transistor to bring said body terminal to a first reference potential; and

a third MOS transistor coupled to said body terminal to bring said body terminal of said first MOS transistor to a second reference potential, said second reference potential provided by a body bias voltage supply to establish a predetermined current enhancement ratio (CER);

said control circuit controlling leakage of said first MOS transistor;

wherein said second transistor'"'"'s gate is controlled by a digital voltage source having a same polarity as that of an output of said CMOS logic gate, and said third transistor controlled by a digital voltage source having a same polarity as that of an input to said CMOS logic gate.

10. The circuit of claim 9, wherein said CER expresses ratio between a current of said drain of said first MOS transistor with body bias to a current of said drain of said first MOS transistor without body bias.

11. The circuit of claim 9, wherein said first MOS transistor is any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

12. The circuit of claim 9, wherein said CER expresses a ratio of width over length of a reference current transistor and width over length of an adaptive body bias transistor, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of said current mirror circuit of said body bias voltage supply.

13. The circuit of claim 9, wherein said MOS device comprises a portion of a logic gate.

14. The circuit of claim 13, wherein said logic gate comprises any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.

15. The circuit of claim 9, wherein said control circuit is connected to at least one other MOS transistor of the same type of said MOS transistor.

16. The circuit of claim 9, further comprising:

a voltage shifter coupled between a drain terminal of said third transistor and said body bias voltage supply.

17. The circuit of claim 9, further comprising:

a voltage shifter coupled between a source terminal of said third transistor and a drain terminal of said second transistor.

18. The circuit of claim 9, further comprising:

a capacitor coupled between a gate terminal of said third transistor and a source terminal of said third transistor.

19. A body voltage control circuit for controlling leakage of a metal-oxide semiconductor (MOS) transistor, comprising:

a first transistor coupled to a body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential;

a second transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential; and

a body bias voltage supply coupled to said second transistor to establish a predetermined current enhancement ratio (CER);

wherein said first transistor'"'"'s gate is controlled by a digital voltage source having a same polarity as that of an output of said CMOS logic gate and said second transistor controlled by a digital voltage source having a same polarity as that of an input to said CMOS logic gate.

20. The circuit of claim 19, wherein said CER expresses a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.

21. The circuit of claim 19, wherein the MOS transistor comprises any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

22. The claim 19, wherein said CER expresses a ratio of width over length of a reference current device and width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

23. The circuit of claim 19, further coupled to at least a second MOS transistor to control leakage of said second MOS transistor.

24. The circuit of claim 19, further comprising:

a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.

25. The circuit of claim 19, further comprising:

a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.

26. The circuit of claim 19, further comprising:

a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.

27. A method of manufacturing a leakage control circuit to control leakage of a metal-oxide semiconductor (MOS) transistor comprising the steps of:

forming the MOS transistor on a substrate, the MOS transistor having a gate terminal, a drain terminal, a source terminal, and a body terminal;

forming a first MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential;

forming a second MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential;

providing a first digital control voltage to said first MOS transistor, said first digital control voltage having an opposite polarity of that of the input signal to said MOS transistor; and

providing a second digital control voltage to said first MOS transistor that has a same polarity as that of the input signal of said MOS transistor;

said second reference potential provided by a body bias voltage supply comprising a bias voltage that establishes a predetermined current enhancement ratio (CER).

28. The method of claim 27, further comprising the step of:

expressing said current enhancement ratio (CER) as the ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.

29. The method of claim 27, further comprising the step of:

expressing said CER as a ratio of width over length of a reference current device and width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

30. The method of claim 27, said MOS device comprising any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

31. The method of claim 27, further comprising the step of:

forming a connection between the leakage control circuit of claim 27 and a second MOS transistor to control leakage of said second MOS transistor.

32. The method of claim 27, further comprising the step of:

forming a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.

33. The method of claim 27, further comprising the step of:

forming a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.

34. The method of claim 27, further comprising the step of:

forming a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.