Method and Apparatus for MOSFET Drain-Source Leakage Reduction
First Claim
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1. A leakage control circuit for a complementary metal-oxide semiconductor (CMOS) gate, comprising:
- a CMOS logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal; and
a control circuit coupled to said CMOS logic gate via any of said first NMOS transistor and said PMOS transistor, said control circuit comprising;
a first transistor coupled to the body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a first reference potential; and
a second transistor coupled to said body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a second reference potential, said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER).
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Abstract
A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits.
74 Citations
39 Claims
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1. A leakage control circuit for a complementary metal-oxide semiconductor (CMOS) gate, comprising:
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a CMOS logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal; and a control circuit coupled to said CMOS logic gate via any of said first NMOS transistor and said PMOS transistor, said control circuit comprising; a first transistor coupled to the body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a first reference potential; and a second transistor coupled to said body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a second reference potential, said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit, comprising:
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a first MOS transistor having a gate terminal, a source terminal, a drain terminal, and a body terminal; and a control circuit coupled to said MOS transistor, said control circuit comprising; a second MOS transistor coupled to said body terminal of said first MOS transistor to bring said body terminal to a first reference potential; and a third MOS transistor coupled to said body terminal of said first MOS transistor to bring said body terminal of said first MOS transistor to a second reference potential, said second reference potential provided by a body bias voltage supply to establish a predetermined current enhancement ratio (CER); said control circuit controlling leakage of said first MOS device. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A body voltage control circuit for controlling leakage of a metal-oxide semiconductor (MOS) transistor, comprising:
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a first transistor coupled to a body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential; a second transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential; and a body bias voltage supply coupled to said second transistor to establish a predetermined current enhancement ratio (CER). - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A method of manufacturing a leakage control circuit to control leakage of a metal-oxide semiconductor (MOS) transistor, comprising the steps of:
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forming the MOS transistor on a substrate, the MOS transistor having a gate terminal, a drain terminal, a source terminal, and a body terminal; forming a first MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential; and forming a second MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential; said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER). - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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35. A method for controlling leakage current of a MOS transistor comprising a gate terminal, a drain terminal, a source terminal and a body terminal, the method comprising the steps of:
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supplying a first reference voltage to the body of the MOS transistor with a control circuit to bring the body terminal of the MOS transistor to a first reference potential; supplying a second reference potential to the body of the MOS transistor with said control circuit to bring the body terminal of the MOS transistor to a second reference potential; and supplying a bias to said control circuit, wherein said second reference potential establishes a predetermined current enhancement ratio (CER). - View Dependent Claims (36, 37, 38, 39)
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Specification