Backside illuminated image sensor with global shutter and storage capacitor

• US 20090201400A1
• Filed: 02/08/2008
• Published: 08/13/2009
• Est. Priority Date: 02/08/2008
• Status: Abandoned Application

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Zhang, Guangbin, Dai, Tiejun, Yang, Hongli
• Application Number:
  US12/028,659
• Publication Number:
  US 20090201400A1
• Time in Patent Office: Days
• US Class Current: 348/296
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A backside illuminated imaging sensor pixel includes a photodiode region, a pixel circuitry region, and a storage capacitor. The photodiode region is disposed within a semiconductor die for accumulating an image charge. The pixel circuitry region is disposed on the semiconductor die between a frontside of the semiconductor die and the photodiode region. The pixel circuitry region overlaps at least a portion of the photodiode region. The storage capacitor is included within the pixel circuitry region overlapping the photodiode region and is selectively coupled to the photodiode region to temporarily store image charges accumulated thereon.

Claims

1. An imaging sensor pixel, comprising:

a photodiode region disposed within a semiconductor die for accumulating an image charge;

a pixel circuitry region disposed within the semiconductor die between a frontside of the semiconductor die and the photodiode region, the pixel circuitry region overlapping at least a portion of the photodiode region;

an interlinking diffusion region disposed within the semiconductor die, the interlinking diffusion region coupled to the photodiode region and extending towards the frontside of the semiconductor die; and

a storage capacitor included within the pixel circuitry region overlapping the photodiode region and selectively coupled via the interlinking diffusion region to the photodiode region to temporarily store the image charge accumulated thereon.

2. The imaging sensor pixel of claim 1, wherein the imaging sensor pixel comprises a complimentary metal-oxide-semiconductor (“

CMOS”

) backside illuminated imaging sensor pixel.

3. The imaging sensor pixel of claim 2, wherein the semiconductor die comprises a P-type silicon substrate and the pixel circuitry region comprises a P-well diffusion region disposed between the photodiode region and the frontside of the semiconductor die.

4. The imaging sensor pixel of claim 1, wherein the storage capacitor comprises:

a first electrode selectively coupled to the interlinking diffusion region;

a second electrode; and

a dielectric insulating layer disposed between the first and second electrodes.

5. The imaging sensor pixel of claim 4, wherein the first and second electrodes are made of a material selected from a group including polysilicon or metal.

6. The imaging sensor pixel of claim 4, wherein the storage capacitor comprises a multilayer stacked capacitor having at least two overlapping dielectric insulating layers.

7. The imaging sensor pixel of claim 4, further comprising:

a grounding diffusion region disposed within the pixel circuitry region and coupled to the second electrode to ground the second electrode, the grounding diffusion region having a same conductivity type as a substrate of the semiconductor die; and

a floating diffusion disposed within the pixel circuitry region and coupled to the first electrode, the floating diffusion having an opposite conductivity type as the substrate.

8. The imaging sensor pixel of claim 7, wherein the imaging sensor pixel comprises a four transistor (“

4T”

) pixel design having all four transistors disposed within the pixel circuitry region, the 4T pixel design comprising;

a transfer transistor coupled between the interlinking diffusion region and the floating diffusion;

a reset transistor coupled to the first electrode to reset the storage capacitor and the floating diffusion;

a source-follower transistor coupled to output the image charge from the storage capacitor; and

a select transistor to select the imaging sensor pixel from other imaging sensor pixels for readout.

9. The imaging sensor pixel of claim 2, further comprising:

a microlens disposed on a backside of the semiconductor die below the photodiode region and optically aligned to focus light received from the backside onto the photodiode region; and

a color filter disposed between the microlens and the photodiode region to filter the light.

10. A method of operation of a pixel array including a plurality of pixels wherein each of the pixels includes a backside illuminated complimentary metal-oxide-semiconductor (“

CMOS”

) imaging sensor, for each of the pixels, the method comprising;

accumulating charge within a photodiode region of the pixel generated by light incident upon a backside of the pixel; and

transferring the charge accumulated within the photodiode region to a storage capacitor, wherein the storage capacitor is positioned on a frontside of the pixel opposite the backside and overlaps the photodiode region.

11. The method of claim 10, further comprising for each pixel:

resetting the photodiode region and the storage capacitor prior to accumulating the charge by temporarily enabling a transfer transistor coupled between the photodiode region and a first electrode of the storage capacitor and by temporarily enabling a reset capacitor coupled between a voltage rail and the first electrode of the storage capacitor; and

resetting the storage capacitor again between accumulating the charge and transferring the charge to the storage capacitor by enabling the reset capacitor while disabling the transfer transistor.

12. The method of claim 11, further comprising for each pixel:

reading out the charge stored on the storage capacitor by temporarily enabling a select transistor.

13. The method of claim 10, wherein transferring the charge accumulated within the photodiode region for each pixel comprises enabling a global shutter signal to commence transferring the charge simultaneously for all pixels within the pixel array.

14. The method of claim 10, further comprising:

focusing the light onto the photodiode region with a microlens disposed on the backside;

grounding a first electrode of the storage capacitor to a grounding diffusion formed in a doped well disposed in an epitaxial layer,

wherein transferring the charge accumulated within the photodiode region to the storage capacitor includes transferring the charge through a transfer gate to a floating diffusion disposed within the doped well having an opposite conductivity type as the doped well, the floating diffusion coupled to a second electrode of the storage capacitor,

wherein the doped well is disposed within the epitaxial layer overlapping the photodiode region between a frontside of the pixel and the photodiode region.

15. An imaging system comprising:

a backside illuminated array of imaging pixels wherein each imaging pixel includes;

a photodiode region for accumulating an image charge;

a storage capacitor coupled to temporarily store the image charge accumulated by the photodiode, the storage capacitor disposed between a frontside of the imaging pixel and the photodiode region;

a transfer transistor to selectively couple the photodiode region to the storage capacitor;

control circuitry coupled to the backside illuminated array of imaging pixels to generate a shutter signal for selectively enabling the transfer transistor of one or more of the imaging pixels; and

readout circuitry coupled to the backside illuminated array of imaging pixels to selectively readout the image charge.

16. The imaging system of claim 15, wherein the shutter signal comprises a global shutter signal coupled to simultaneously enable each transfer transistor within the backside illuminated array of imaging pixels to simultaneously capture an image with all the imaging pixels.

17. The imaging system of claim 15, wherein the storage capacitor and transfer transistor are disposed within a diffusion well formed over the photodiode region, wherein each imaging pixel further includes:

a floating diffusion having an opposite conductivity type as the diffusion well coupled to the transfer transistor and coupled to a first electrode of the storage capacitor; and

a grounding diffusion having a similar conductivity type as the diffusion well coupled to a second electrode of the storage capacitor.

18. The imaging system of claim 15, wherein the backside illuminated array of imaging pixels further includes:

a plurality of microlenses disposed on a backside of the array of imaging pixels and each aligned to focus light on a corresponding pixel; and

a metal stack including two or more metal layers disposed on a frontside of the array of imaging pixels for routing signals.

19. The imaging system of claim 15, wherein the storage capacitor comprises a multilayer stacked capacitor having at least two overlapping dielectric insulating layers.

20. The imaging system of claim 15, wherein each pixel comprises a four transistor (“

4T”

) pixel design including;

the transfer transistor coupled between the photodiode region and a floating diffusion;

a reset transistor coupled to a first electrode of the storage capacitor to reset the image charge on the storage capacitor;

a source-follower transistor coupled to output the image charge from the storage capacitor; and

a select transistor to select the imaging sensor pixel from other imaging sensor pixels for readout.