METHOD AND APPARATUS OF BINARIZING INPUT SIGNAL, DISC DRIVER AND RECORDING MEDIUM

• US 20090202023A1
• Filed: 06/04/2007
• Published: 08/13/2009
• Est. Priority Date: 07/27/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Hyun-Soo
• Granted Patent: US 8,249,200 B2
• Time in Patent Office: Days
• US Class Current: 375/341
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/10296 using the Viterbi algorithm
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors

Abstract

A method and an apparatus are provided for binarizing an input signal, which is capable of reliably correcting an offset of the input signal even when the input signal does not reach a reference level or has a single frequency, a disc driver and a recording medium. The binarizing method includes viterbi-decoding the input signal to obtain a viterbi-decoded signal; slicing the input signal based on a predetermined reference level to obtain a sliced signal; obtaining an offset of the input signal by low-pass filtering the viterbi-decoded signal or the sliced signal; and correcting the offset of the input signal based on the obtained offset. The viterbi-decoded signal is a binary signal of the input signal.

Claims

1. A method of binarizing an input signal, comprising:

viterbi-decoding the input signal;

slicing the input signal based on a predetermined reference level;

obtaining an offset of the input signal; and

correcting the offset of the input signal based on the obtained offset;

wherein the viterbi-decoded signal is a binary signal of the input signal.

2. The method of claim 1, wherein the obtaining of the offset comprises:

comparing the viterbi-decoded signal with the sliced signal;

low-pass filtering the viterbi-decoded signal to obtain the offset if the viterbi-decoded signal is not identical to the sliced signal; and

low-pass filtering the sliced signal to obtain the offset if the viterbi-decoded signal is identical to the sliced signal.

3. The method of claim 2, wherein the comparing of the viterbi-decoded signal with the sliced signal is performed in synchronization with a system clock.

4. The method of claim 3, wherein the system clock is generated based on the input signal from which the offset is removed.

5. The method of claim 1, wherein the input signal, which will be viterbi-decoded or sliced, is subjected to the offset correction.

6. The method of claim 1, wherein the viterbi-decoding of the input signal further comprises pre-processing the input signal into a signal for the viterbi decoding.

7. The method of claim 6, wherein the pre-processing of the input signal comprises equalizing the input signal.

15. The method of claim 1, wherein the obtaining of the offset of the input signal comprises:

low-pass filtering the viterbi-decoded input signal so as to obtain the offset of the input signal, if the viterbi-decoded input signal is not identical to the sliced input signal;

low-pass filtering the sliced input signal so as to obtain the offset of the input signal, if the viterbi-decoded input signal is identical to the sliced input signal.

16. The method of claim 15, further comprising:

binarizing the input signal based on the corrected offset, so as to generate an output signal.

17. The method of claim 1, wherein:

the viterbi-decoding of the input signal is performed based on a system clock signal;

the slicing the input signal is performed based on the predetermined reference level and the system clock signal; and

the obtaining of the offset of the input signal comprises;

low-pass filtering the viterbi-decoded input signal so as to obtain the offset of the input signal, if a resolution of the input signal is higher than a resolution of the system clock signal; and

low-pass filtering the sliced input signal so as to obtain the offset of the input signal, if the resolution of the input signal is not higher than the resolution of the system clock signal.

18. The method of claim 17, wherein the system clock signal is generated based on the corrected input signal.

19. The method of claim 17, wherein:

the low-pass filtering of the viterbi-decoded input signal is synchronized with the system clock signal; and

the low-pass filtering of the sliced input signal is synchronized with the system clock signal.

20. The method of claim 17, further comprising binarizing the input signal based on the corrected offset, so as to generate an output signal.

8. An apparatus to binarize an input signal, comprising:

a viterbi-decoder to viterbi-decode the input signal;

a slicer to slice the input signal based on a predetermined reference level;

a low pass filter module to low-pass filter an output signal of the viterbi decoder or an output signal of the slicer;

an offset correcting module to remove an output signal of the low pass filter module from the input signal, to correct an offset of the input signal, and to supply the input signal with the corrected offset to the viterbi decoder and the slicer,

wherein the output signal of the viterbi decoder is a binary signal of the input signal.

9. The apparatus of claim 8, wherein the low pass filter module comprises:

a selector to select the output signal of the viterbi decoder or the output signal of the slicer; and

a low pass filter to low-pass filter a signal output from the selector.

10. The apparatus of claim 9, wherein the selector selects and outputs the output signal of the slicer when the output signal of the viterbi decoder is identical to the output signal of the slicer, and selects and outputs the output signal of the viterbi decoder when the output signal of the viterbi decoder is not identical to the output signal of the slicer.

11. The apparatus of claim 8, further comprising a system clock signal generate module to generated a system clock signal using the signal output from the offset correcting module and to supply the system clock signal to the viterbi decoder and the low pass filter module.

12. The apparatus of claim 8, further comprising a preprocessor to convert the signal output from the offset correcting module into a signal having a shape necessary for the viterbi decoder.

13. A disc driver having a function of binarizing an RF (radio frequency) signal read from a disc, the disc driver comprising:

a viterbi decoder to viterbi-decode the RF signal read from the disc;

a slicer to slice the RF signal using a predetermined reference level;

a low pass filter module to low-pass filter a signal output from the viterbi decoder or a signal output from the slicer; and

an offset correcting module to remove a signal output from the low pass filter module from the RF signal, to correct an offset of the RF signal, and to provide the RF signal with the corrected offset to the viterbi decoder and the slicer;

wherein the signal output from the viterbi decoder is a binary signal of the RF signal.

14. A computer-readable recording medium having embodied thereon a computer program to perform a method of binarizing an input signal, the method comprising:

viterbi-decoding the input signal to obtain a viterbi-decoded signal;

slicing the input signal based on a predetermined reference level to obtain a sliced signal;

low-pass filtering the viterbi-decoded signal or the sliced signal to obtain an offset of the input signal; and

correcting the offset of the input signal using the obtained offset;

wherein the viterbi-decoded signal is a binary signal of the input signal.