Strained Gate Electrodes in Semiconductor Devices

• US 20090203202A1
• Filed: 03/13/2009
• Published: 08/13/2009
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Chien-Chao Huang, Fu-Liang Yang
• Original Assignee: Chien-Chao Huang, Fu-Liang Yang
• Inventors: Yang, Fu-Liang, Huang, Chien-Chao
• Granted Patent: US 8,835,291 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

Claims

1. A method of forming an integrated circuit, the method comprising:

providing a substrate;

forming a gate dielectric layer over the substrate;

forming a gate electrode layer over the gate dielectric layer; and

amorphizing at least a portion of the gate electrode layer, thereby creating an amorphized gate electrode layer.

2. The method of claim 1, wherein a thickness of the gate electrode layer is completely amorphized during the amorphizing.

3. The method of claim 1, wherein the amorphizing is performed at least in part by an implantation.

4. The method of claim 1, further comprising forming a cap layer over the amorphized gate electrode layer.

5. The method of claim 1, further comprising recrystallizing the amorphized gate electrode layer.

6. The method of claim 5, wherein the recrystallizing the amorphized gate electrode layer is performed at least in part by annealing.

7. The method of claim 1, further comprising forming a glue layer interposed between the gate dielectric layer and the gate electrode layer.

8. The method of claim 1, further comprising forming a stress layer interposed between the gate dielectric layer and the gate electrode layer.

9. A method of forming an integrated circuit, the method comprising:

providing a substrate;

forming a gate dielectric layer over the substrate;

forming a gate electrode layer over the gate dielectric layer;

amorphizing at least a portion of the gate electrode layer, thereby creating an amorphized gate electrode layer;

forming a cap layer over the gate electrode layer; and

crystallizing at least a portion of the amorphized gate electrode layer.

10. The method of claim 9, further comprising forming a mask layer over at least a portion of the gate electrode layer prior to the amorphizing, the mask layer reducing the amorphizing of the gate electrode layer underlying the mask layer.

11. The method of claim 9, wherein a thickness of the gate electrode layer is completely amorphized during the amorphizing.

12. The method of claim 9, wherein the amorphizing is performed at least in part by an implantation.

13. The method of claim 9, wherein the crystallizing is performed at least in part by annealing.

14. A method of forming an integrated circuit, the method comprising:

providing a substrate, the substrate having a first section and a second section;

forming a dielectric layer over the substrate in the first section and the second section;

forming a first layer over the dielectric layer in the first section and the second section;

forming a mask layer over the first layer in the first section;

amorphizing at least a portion of the first layer in the second section;

removing the mask layer;

forming a cap layer over the first layer in the first section and the second section; and

at least partially crystallizing the amorphized portion of the first layer.

15. The method of claim 14, further comprising forming a first transistor in the first section and a second transistor in the second section, wherein the dielectric layer and the first layer are used to form a gate dielectric and a gate electrode for each of the first transistor and the second transistor.

16. The method of claim 15, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

17. The method of claim 14, wherein the amorphizing creates an amorphized layer and an un-amorphized layer, the un-amorphized layer being thicker than the amorphized layer.

18. The method of claim 17, wherein the amorphized layer is about 0.2 to about 0.5 times a thickness of the un-amorphized layer.

19. The method of claim 14, further comprising forming a glue layer interposed between the gate dielectric layer and the first layer.

20. The method of claim 14, further comprising forming a stress layer interposed between the gate dielectric layer and the first layer.