Integated circuits and methods to control access to multiple layers of memory

• US 20090204777A1
• Filed: 02/07/2008
• Published: 08/13/2009
• Est. Priority Date: 03/30/2005
• Status: Active Grant

• Current Assignee: Hefei Reliance Memory Limited
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Granted Patent: US 9,058,300 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Claims

1. A memory access control circuit, comprising:

a memory access circuit including a permissions list repository configured to store access control data in a third dimension memory for an address; and

an access detector responsive to the access control data, the access detector configured to detect the address for accessing a memory location in the third dimension memory and configured to generate an access disable signal configured to disable access to the memory location.

2. The circuit of claim 1, wherein the memory access circuit is further configured to disable the access to the memory location substantially in parallel to detecting the address for the memory location.

3. The circuit of claim 1 and further comprising:

a first portion formed in a logic layer and a second portion formed in one or more layers in the third dimension memory.

4. The circuit of claim 3, wherein the first portion comprises at least a portion of the access detector and the second portion includes the permissions list repository.

5. The circuit of claim 3, wherein the first portion further comprises at least a portion of an access override controller and the second portion further comprises a permissions override list repository.

6. The circuit of claim 3, wherein the second portion further comprises a configuration register configured to store a password.

7. The circuit of claim 3, wherein the first portion and the second portion are formed using a CMOS fabrication process.

8. The circuit of claim 1, wherein the access control data further comprises either write control data for either permitting or prohibiting a write operation to the memory location, or read control data for either permitting or prohibiting a read operation from the memory location, or both.

9. The circuit of claim 1 and further comprising:

an access interrupter configured to interrupt application of an access voltage to a main array of the third dimension memory;

a permissions override access repository configured to store override control data in the third dimension memory for overriding the access control data; and

an override access controller configured to generate an override signal to control the access interrupter.

10. The circuit of claim 1 and further comprising:

a column access unit; and

a row access unit,

the column and row access units are configured to access a subset of the third dimension memory in the permissions list repository for either writing or reading the access control data for the address.

11. The circuit of claim 10, wherein the column access unit and the row access unit are responsive to a most significant bit in the address for programming the permission list repository with the access control data.

12. The circuit of claim 10 and further comprising:

an access control chip select port for programming the permission list repository with the access control data.

13. The circuit of claim 1, wherein the access disable signal further comprises either a read disable signal, or a write disable signal, or both.

14. A memory access control circuit, comprising:

a substrate;

a logic layer formed on the substrate;

a third dimension memory positioned on top of the logic layer, the third dimension memory including an access control memory including subsets of third dimension memory cells configured to store portions of a permissions list; and

an interface configured to provide control signals, address signals, and data signals to the third dimension memory for accessing the access control memory,

wherein the subsets of the third dimension memory cells store access control data at a vertical displacement from the logic layer.

15. The circuit of claim 14, wherein the logic layer further comprises an access detector.

16. The circuit of claim 14, wherein the interface further comprises at least one interface type selected from the group consisting of a NAND-type interface, a NOR-type interface, a DRAM interface, and a SRAM interface.

17. The circuit of claim 14, wherein the interface further comprises a select signal terminal configured to select the access control memory for programming.

18. The circuit of claim 14 and further comprising:

an address decoder configured to generate a most significant bit (MSB) of an address, wherein the MSB is configured to enable programming of the permissions list.

19. The circuit of claim 14 and further comprising:

an access override controller including password registers for generating a signal for enabling a write operation to a permissions override list repository upon matching password values; and

a master lockout register configured to prevent updates to a configuration memory.

20. A method for controlling access operations to a memory, comprising:

detecting an access operation in relation to a first memory location in a first plane of memory in multiple layers of third dimension memory; and

accessing a second memory location in a second plane of memory in the multiple layers of third dimension memory to determine whether to restrict the access operation.

21. The method of claim 20, wherein the accessing the second memory location further comprises

decoding an address for the first memory location in a logic layer to form a decoded address in response to the access operation, and

applying the decoded address to the second plane.

22. The method of claim 20 and further comprising:

performing either a write operation or a read operation, or both, as the access operation.

23. The method of claim 22 and further comprising:

reading the access control data in the second memory location; and

disabling either the write operation or the read operation, or both, in response to the access control data.

24. The method of claim 22, wherein the write operation does not require an erase operation prior to the write operation.

25. The method of claim 20 and further comprising:

specifying an address for the memory location to modify access to the memory location; and

associating the address with the access control data to specify whether to disable either writing or reading, or both, for the memory location.

26. The method of claim 25 and further comprising:

storing the access control data for the address as data representing a permissions list.

27. The method of claim 20 and further comprising:

forming at least a portion of an access detector; and

forming the multiple layers of third dimension memory on top of a logic layer, the multiple layers of third dimension memory including third dimension memory cells.