MICROPROCESSOR WITH MICROARCHITECTURE FOR EFFICIENTLY EXECUTING READ/MODIFY/WRITE MEMORY OPERAND INSTRUCTIONS

• US 20090204800A1
• Filed: 04/10/2008
• Published: 08/13/2009
• Est. Priority Date: 02/08/2008
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Eddy, Colin, Col, Gerard M., Hooker, Rodney E.
• Granted Patent: US 8,069,340 B2
• Time in Patent Office: Days
• US Class Current: 712/245
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags

Abstract

The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location.

Claims

1. A microprocessor having a macroinstruction set in its macroarchitecture that includes a macroinstruction that instructs the microprocessor to perform a read/modify/write operation on an operand in memory, the microprocessor comprising:

an instruction translator, configured to translate the macroinstruction into exactly three microinstructions to perform the read/modify/write operation on the memory operand, wherein the three microinstructions are first, second, and third microinstructions;

wherein the first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location;

wherein the second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result;

wherein the third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction;

a first execution unit, configured to receive the first microinstruction, to responsively load the memory operand into the microprocessor from the memory location; and

a second execution unit, configured to also receive the first microinstruction, to responsively calculate the destination address of the memory location, wherein the first and second execution units are distinct execution units within the microprocessor.

2. The microprocessor of claim 1, wherein the instruction translator is configured to output at most three microinstructions per clock cycle.

3. The microprocessor of claim 1, wherein the instruction translator is configured to output more than three microinstructions per clock cycle, wherein the instruction translator is configured to translate a second macroinstruction into a fourth microinstruction during a same clock cycle as the instruction translator translates the first macroinstruction into the exactly three microinstructions.

4. The microprocessor of claim 1, further comprising:

a reorder buffer, coupled to the instruction translator and to the first and second execution units, configured to store the first microinstruction into a single entry of the reorder buffer even though the first microinstruction is executed by both the first and second execution units.

5. The microprocessor of claim 4, wherein each of the first and second execution units is further configured to subsequently provide a respective indication that the first microinstruction has been executed.

6. The microprocessor of claim 5, wherein the reorder buffer is configured to retire the first microinstruction only after receiving from both of first and second execution units the respective indications that the first microinstruction has been executed.

7. The microprocessor of claim 4, wherein the single entry of the reorder buffer includes a flag indicating the first microinstruction is of a type of microinstruction of a microinstruction set of the microprocessor to be executed by both the first and second execution units of the microprocessor.

8. The microprocessor of claim 1, wherein the microprocessor refrains from invoking a microinstruction sequence in a microinstruction ROM to execute the macroinstruction.

9. The microprocessor of claim 1, further comprising:

a third execution unit, configured to modify the loaded memory operand to generate a result.

10. The microprocessor of claim 9, further comprising:

a fourth execution unit, configured to write the result to the memory location whose destination address is calculated by the first microinstruction.

11. A method for executing a macroinstruction in a microprocessor having a macroinstruction set in its macroarchitecture that includes the macroinstruction that instructs the microprocessor to perform a read/modify/write operation on an operand in memory, the method comprising:

translating the macroinstruction into exactly three microinstructions to perform the read/modify/write operation on the memory operand, wherein the three microinstructions are first, second, and third microinstructions;

wherein the first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location;

wherein the second microinstruction instructs the microprocessor to modify the loaded memory operand to generate a result;

wherein the third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction;

receiving the first microinstruction by both first and second execution units of the microprocessor;

loading the memory operand into the microprocessor from the memory location, wherein said loading is performed by a first execution unit of the microprocessor in response to said receiving; and

calculating the destination address of the memory location, wherein said calculating is performed by a second execution unit of the microprocessor in response to said receiving, wherein the first and second execution units are distinct execution units within the microprocessor.

12. The method of claim 11, wherein said translating is performed by an instruction translator of the microprocessor, wherein the instruction translator is configured to output at most three microinstructions per clock cycle.

13. The method of claim 11, wherein said translating is performed by an instruction translator of the microprocessor, wherein the instruction translator is configured to output more than three microinstructions per clock cycle, the method further comprising:

translating a second macroinstruction into a fourth microinstruction during the same clock cycle as the instruction translator translates the first macroinstruction into the exactly three microinstructions.

14. The method of claim 11, further comprising:

storing the first microinstruction into a single entry of a reorder buffer of the microprocessor even though the first microinstruction is executed by both the first and second execution units.

15. The method of claim 14, further comprising:

providing a first indication that the first microinstruction has been executed subsequent to said loading, wherein said providing the first indication is performed by the first execution unit;

providing a second indication that the first microinstruction has been executed subsequent to said calculating, wherein said providing the second indication is performed by the second execution unit.

16. The method of claim 15, further comprising:

retiring the first microinstruction only after receiving both the first and second indications that the first microinstruction has been executed.

17. The method of claim 14, wherein the single entry of the reorder buffer includes a flag indicating the first microinstruction is of a type of microinstruction of a microinstruction set of the microprocessor to be executed by both the first and second execution units of the microprocessor.

18. The method of claim 11, wherein the microprocessor refrains from invoking a microinstruction sequence in a microinstruction ROM to execute the macroinstruction.

19. A microprocessor having a macroinstruction set in its macroarchitecture that includes a macroinstruction that instructs the microprocessor to perform a read/modify/write operation on a memory operand having an address, the microprocessor comprising:

a cache memory, configured to cache data including the memory operand;

an instruction translator, configured to translate the macroinstruction into exactly three microinstructions to perform the read/modify/write operation on the memory operand, wherein the three microinstructions are first, second, and third microinstructions;

a first execution unit, configured to load the operand from the cache memory into a register of the microprocessor in response to the first microinstruction;

a second execution unit, configured to calculate the address of the memory operand also in response to the first microinstruction;

a third execution unit, configured to perform an arithmetic or logical operation on the operand from the register to generate a result in response to the second microinstruction after the first execution unit loads the operand from cache memory; and

a fourth execution unit, configured to store the result to the cache memory at the address calculated by the second execution unit in response to the third microinstruction;

wherein the first, second, third, and fourth execution units are distinct execution units within the microprocessor.

20. The microprocessor of claim 19, further comprising:

a memory subsystem, coupled to the instruction translator, configured to allocate a store buffer of the microprocessor in response to the first microinstruction;

wherein the second execution unit is further configured to write the calculated address of the memory operand to the allocated store buffer in response to the first microinstruction.

21. A microprocessor having a macroinstruction set in its macroarchitecture that includes a macroinstruction that instructs the microprocessor to perform a read/modify/write operation on an operand in memory, the microprocessor comprising:

an instruction translator, configured to translate the macroinstruction into a plurality of microinstructions to perform the read/modify/write operation on the memory operand;

first and second execution units, each configured to receive a first of the plurality of microinstructions, wherein the first execution unit is configured to execute the read operation on the memory operand, wherein the second execution unit is configured to execute the write operation on the memory operand, wherein the first and second execution units are distinct execution units within the microprocessor; and

a reorder buffer, coupled to the instruction translator and to the first and second execution units, having a plurality of entries for storing microinstructions, wherein the microprocessor allocates a single entry configured to store the first microinstruction even though both of the first and second execution units receive and execute the first microinstruction.

22. The microprocessor of claim 21, wherein each of the first and second execution units is configured to provide to the reorder buffer a respective indication that it has executed the first microinstruction.

23. The microprocessor of claim 21, wherein each of the plurality of entries of the reorder buffer includes a flag for indicating whether the microinstruction stored in the entry is of a type of the first microinstruction that must be executed by more than one execution unit.

24. The microprocessor of claim 23, wherein the reorder buffer is configured to wait to retire the microinstruction stored in the entry if the flag indicates the microinstruction is of a type of the first microinstruction that must be executed by more than one execution unit.

25. A microprocessor having a macroinstruction set in its macroarchitecture that includes a macroinstruction that instructs the microprocessor to perform a read/modify/write operation on a memory operand having an address, the microprocessor comprising:

an instruction translator, configured to translate the macroinstruction into exactly three microinstructions to perform the read/modify/write operation on the memory operand;

a first execution unit, exclusively configured among all the execution units of the microprocessor to calculate read operation addresses of memory operands; and

a second execution unit, exclusively configured among all the execution units of the microprocessor to calculate write operation addresses of memory operands, wherein the first and second execution units are distinct execution units within the microprocessor; and

wherein the microprocessor is configured to dispatch one of the three microinstructions to the first execution unit to calculate the read operation address of the memory operand, and to also dispatch the one of the three microinstructions to the second execution unit to calculate the write operation address of the memory operand.