POWER MANAGEMENT WITH DYNAMIC FREQUENCY DAJUSTMENTS
First Claim
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1. A system for adjusting clock frequency, said system comprising:
- a device operable for executing a task; and
a processor coupled to said device, wherein said processor specifies a first frequency for a clock signal used by said device and thereafter is placed in a reduced power mode;
wherein said device is operable to perform said task after said processor is placed in said reduced power mode until a triggering event causes said device to send an interrupt to said processor;
wherein in response to said interrupt said processor awakens to dynamically adjust a frequency of said clock signal so that a metric satisfies a first condition, and wherein if said frequency returns to said first frequency then said processor is again placed in said reduced power mode.
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Abstract
A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
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Citations
20 Claims
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1. A system for adjusting clock frequency, said system comprising:
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a device operable for executing a task; and a processor coupled to said device, wherein said processor specifies a first frequency for a clock signal used by said device and thereafter is placed in a reduced power mode;
wherein said device is operable to perform said task after said processor is placed in said reduced power mode until a triggering event causes said device to send an interrupt to said processor;
wherein in response to said interrupt said processor awakens to dynamically adjust a frequency of said clock signal so that a metric satisfies a first condition, and wherein if said frequency returns to said first frequency then said processor is again placed in said reduced power mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of managing power consumption in an electronic system, said method comprising:
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with a processor operating in a first power mode, selecting a device to perform a task and selecting a first frequency for a clock used by said device; entering a reduced power mode at said processor after said device and said first frequency are selected, wherein a frequency of said clock remains set to said first frequency until a triggering event causes said device to send an interrupt to said processor; awakening said processor in response to said interrupt so that said processor can dynamically adjust said frequency; and re-entering said reduced power mode at said processor if said frequency is adjusted to said first frequency. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of managing power consumption in an electronic system, said method comprising:
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with a processor in a reduced power mode, operating a device to perform a task using a clock signal having a frequency set to a first frequency; sending an interrupt to said processor in response to a triggering event, wherein said triggering event indicates a requirement to increase said frequency of said clock signal, wherein said interrupt causes said processor to exit said reduced power mode; subsequent to said interrupt, increasing said frequency of said clock signal to a second frequency specified by said processor; subsequent to increasing said frequency of said clock signal, monitoring a metric associated with said device; and comparing said metric to a threshold and adjusting said frequency of said clock signal based on a result of said comparing. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification