GLOBAL HARDWARE SUPERVISED POWER TRANSITION MANAGEMENT CIRCUITS, PROCESSES AND SYSTEMS
First Claim
1. An electronic circuit comprisinga bus;
- a peripheral coupled to said bus, the peripheral having a storing circuit for a succession-presetting and a parameter setting currently-effective for peripheral operation on said bus; and
a power management circuit operable in response to a power management transition request to send a first signal to said peripheral, and to initiate a bus frequency transition, and to send a second signal to the peripheral after the bus frequency transition, andsaid peripheral is responsive to the first signal to stall peripheral operation on said bus, said peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on said bus are stalled and responsive to the second signal to re-enable peripheral operation on said bus.
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Accused Products
Abstract
An electronic circuit including a bus (3521), a peripheral (3510.i/3552.1) coupled to the bus (3521), the peripheral having a storing circuit (3620.i, 3625.i) for a succession-presetting and a parameter setting currently-effective for peripheral operation on the bus (3521); and a power management circuit (3570) operable in response to a power management transition request (GO_bit) to send a first signal (START_bit_i) to the peripheral, and to initiate a bus frequency transition, and to send a second signal (PER_ENABLE_i) to the peripheral after the bus frequency transition; and the peripheral is responsive to the first signal (START_bit_i) to stall peripheral operation on the bus (3521), the peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on the bus (3521) are stalled and responsive to the second signal (PER_ENABLE_i) to re-enable peripheral operation on the bus (3521). Other circuits, devices, systems, apparatus, and processes are disclosed.
123 Citations
22 Claims
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1. An electronic circuit comprising
a bus; -
a peripheral coupled to said bus, the peripheral having a storing circuit for a succession-presetting and a parameter setting currently-effective for peripheral operation on said bus; and a power management circuit operable in response to a power management transition request to send a first signal to said peripheral, and to initiate a bus frequency transition, and to send a second signal to the peripheral after the bus frequency transition, and said peripheral is responsive to the first signal to stall peripheral operation on said bus, said peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on said bus are stalled and responsive to the second signal to re-enable peripheral operation on said bus. - View Dependent Claims (2, 3, 4, 7, 8, 9, 10)
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- 5. The electronic circuit claimed in 1 wherein said storing circuit includes a buffer, and said peripheral is operable to continue peripheral operations with said buffer regardless of whether peripheral operation on said bus is stalled.
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11. A power management article comprising:
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an input for a power management transition request; an output for a transition initiation signal; an input for a transition initiation acknowledgment; an output for a frequency control; an input for a frequency stabilization signal; an output for a transition completion signal; and a state machine responsive to the input for the power management transition request to activate the output for a transition initiation signal and then responsive to the input for the transition initiation acknowledgment to activate the output for the frequency control and then responsive to the input for the frequency stabilization signal to activate the output for the transition completion signal. - View Dependent Claims (12, 13)
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14. An electronic peripheral comprising:
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a functional circuit for establishing peripheral functionality; a bus interface circuit coupled to said storage circuit; a storage circuitry coupled to said functional circuit and to said bus interface circuit, said storage circuit having a data buffer and a space for successively applicable power management related control parameter values; and a peripheral controller responsive to a transition initiation signal to disable at least part of the bus interface circuit, and to transfer current effectiveness between at least two of the successively applicable power management related control parameter values, and responsive to a re-enabling signal to re-enable the disabled part of the bus interface circuit. - View Dependent Claims (15, 16, 17, 18)
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19. An electronic image processing system comprising:
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processing circuitry operable for image processing; a bus coupled to said processing circuitry; an image peripheral coupled to said bus, the image peripheral having a storing circuit for a succession-presetting and a parameter setting currently-effective for image peripheral operation on said bus, said processor operable to pre-program the succession presetting in the image peripheral and to generate a power management transition request; and a power management circuit operable in response to the power management transition request to send a first signal to said image peripheral, and to initiate a bus frequency transition, and to send a second signal to the image peripheral after the bus frequency transition, and said image peripheral is responsive to the first signal to stall image peripheral operation on said bus, said image peripheral operable to automatically promote the succession pre-setting to currently-effective status for the image peripheral after image peripheral operations on said bus are stalled and responsive to the second signal to re-enable image peripheral operation on said bus. - View Dependent Claims (20, 21)
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22. A manufacturing process comprising
preparing design code representing a peripheral having a bus interface and a register field for a current setting related to power management and a register field for a shadow setting related to power management and a power management circuit coupled to the peripheral to stall the bus interface and promote a shadow setting to the current setting, and re-enable the bus interface; - and
making at least one integrated circuit by wafer fabrication responsive to said design code.
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Specification