Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules

• US 20090204872A1
• Filed: 04/21/2009
• Published: 08/13/2009
• Est. Priority Date: 12/02/2003
• Status: Abandoned Application

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, Frank
• Application Number:
  US12/427,675
• Publication Number:
  US 20090204872A1
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Claims

1. A smart storage switch multi-level-controller comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned NVM controller to generate a logical block address (LBA), the virtual storage processor performing a mapping for data striping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and

a logical to physical address mapper, in the NVM controller, that maps the LBA to a physical block address (PBA).

2. The smart storage switch multi-level-controller of claim 1 further comprising:

a flash interface for connecting to a plurality of raw-NAND flash memory chips, the flash interface coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the logical to physical address mapper in the NVM controller;

whereby address mapping is performed to access the raw-NAND flash memory chips.

3. The smart storage switch multi-level-controller of claim 2 further comprising:

a striping unit for distributing data segments of equal size across multiple channels of the plurality of raw-NAND flash memory chips.

4. The smart storage switch multi-level-controller of claim 3 wherein a stripe depth is equal to N times a stripe size, wherein N is a whole number of the plurality of NVM controllers, and wherein the stripe size is equal to a number of pages that are simultaneously writable into one of the plurality of NVM controllers.

5. The smart storage switch multi-level-controller of claim 2 further comprising:

a truncation process, activated on power-up, for determining a smallest size of the plurality of raw-NAND flash memory chips accessible by each NVM controller, and for setting a size of the plurality of raw-NAND flash memory chips accessible by each NVM controller to the smallest size.

6. The smart storage switch multi-level-controller of claim 3 further comprising:

means for monitoring wear-leveling by distributing data segments across multiple channels of the plurality of raw-NAND flash memory chips;

wherein the NVM controller further comprises means for wear leveling data written to the plurality of raw-NAND flash memory chips for even wear across the plurality of raw-NAND flash memory chips.

7. The smart storage switch multi-level-controller of claim 2 further comprising:

a parity unit for generating parity bits for storage with the data segments for redundant storage;

a parity and Error-Correction Code (ECC) circuit for correcting parity-bit errors occurring in data segments in a stripe read from one of the plurality of raw-NAND flash memory chips acting as a channel; and

a flash memory page ECC circuit for detecting and correcting errors occurring inside a flash memory page, wherein ECC codes are stored in a flash page spare area.

8. The smart storage switch multi-level-controller of claim 2 further comprising:

a caching circuit, implemented by the volatile memory buffer to store associated buffer data from the upstream interface, the caching circuit for transaction buffering;

wherein the NVM controller further comprises low-level means for caching data in the plurality of raw-NAND flash memory chips.

9. The smart storage switch multi-level-controller of claim 2 wherein the virtual storage processor further comprises high-level means for mapping the host data into data segments of equal size across multiple channels for storage in the plurality of raw-NAND flash memory chips;

wherein the NVM controller further comprises low-level means for mapping data written to the plurality of raw-NAND flash memory chips for distribution across the plurality of raw-NAND flash memory chips.

10. The smart storage switch multi-level-controller of claim 2 wherein the smart storage transaction manager further comprises:

an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of NVM controllers;

a multi-channel striping unit for distributing groups of data segments of equal size across groups of multiple channels of the plurality of raw-NAND flash memory chips;

whereby the plurality of NVM controllers are accessed in interleaves.

11. The smart storage switch multi-level-controller of claim 2 wherein a non-volatile memory blocks comprise multiple flash die that are stacked together and accessible by interleaving, and wherein each of the multiple flash die comprises two planes that are accessible by interleaving;

wherein a size of the data segment is equal to multiple equal-sized pages per channel, and each channel has one of the plurality of NVM controllers, whereby the host data is striped with a depth to match the plurality of NVM controllers.

12. The smart storage switch multi-level-controller of claim 1 wherein the smart storage transaction manager further comprises:

an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of NVM controller, whereby the plurality of NVM controllers are accessed in interleaves.