SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS

• US 20090204933A1
• Filed: 01/29/2009
• Published: 08/13/2009
• Est. Priority Date: 01/28/2008
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Rezgui, Sana
• Granted Patent: US 8,191,021 B2
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: H03K 19/0033 Radiation hardening

Abstract

A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.

Claims

1. A method for single event transient filtering of an end user logic design, the logic design including design constraints, in a programmable logic integrated circuit device, the device having physical programmable elements and control elements associated with the programmable elements, the method comprising:

(a) converting the end user logic design to virtual programmable elements;

(b) identifying locations requiring SET filters;

(c) generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device; and

(d) creating a data structure for programming the control elements.

2. The method of claim 1, wherein the step of generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device includes:

(a) analyzing the design constraints and the identified locations requiring SET filters; and

(b) determining the type of SET filter to be generated at each identified location.

3. The method of claim 2, wherein the step of generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device includes:

(a) analyzing the mapping; and

(b) if the mapping fails to meet the design constraints;

(i) adjusting the design constraints, and

(ii) repeating the step of generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device.

4. The method of claim 3, further comprising:

programming the programmable logic device with the data structure.

5. The method of claim 2, further comprising:

programming the programmable logic device with the data structure.

6. The method of claim 1, further comprising:

programming the programmable logic device with the data structure.

7. A computer program product in a computer-readable medium for use in a data processing system for programming a programmable logic integrated circuit device with single event transient filtering of an end user logic design, the end user logic design including design constraints, the programmable logic integrated circuit device having physical programmable elements and control elements associated with the physical programmable elements, the computer program product comprising:

(a) first instructions for converting the end user logic design into virtual programmable elements;

(b) second instructions for identifying locations requiring SET filters;

(c) third instructions for generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device; and

(d) fourth instructions for creating a data structure for programming the control elements.

8. The computer program product of claim 7, wherein the third instructions further comprise instructions for:

(a) analyzing the design constraints and the identified locations requiring SET filters; and

(b) determining the type of SET filter to be generated at each identified location.

9. The computer program product of claim 8, wherein the third instructions further comprise instructions for:

(a) analyzing the mapping; and

(b) if the mapping fails to meet the design constraints;

(i) adjusting the design constraints, and

(ii) repeating the third instructions.

10. The computer program product of claim 9, further comprising:

fifth instructions for programming the programmable logic device with the data structure.

11. The computer program product of claim 8, further comprising:

fifth instructions for programming the programmable logic device with the data structure.

12. The computer program product of claim 7, further comprising:

fifth instructions for programming the programmable logic device with the data structure.