METHOD AND DEVICE FOR REDUCING CROSSTALK IN BACK ILLUMINATED IMAGERS

• US 20090206377A1
• Filed: 06/04/2008
• Published: 08/20/2009
• Est. Priority Date: 02/19/2008
• Status: Active Grant

• Current Assignee: SRI International, Inc.
• Original Assignee: SRI International, Inc.
• Inventors: Bhaskaran, Mahalingam, Swain, Pradyumna Kumar
• Granted Patent: US 7,985,612 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A method and resulting device for reducing crosstalk in a back-illuminated imager is disclosed, comprising providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; forming an epitaxial layer substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers; and forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer. The seed layer and the epitaxial layer of the device have a net dopant concentration profile which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.

Claims

1. A method for reducing crosstalk in a back-illuminated imager, comprising the steps of:

providing a substrate comprising

an insulator layer and

a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer;

forming an epitaxial layer substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers; and

forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer.

2. The method of claim 1, further comprising the step of diffusing one or more dopants into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile in the seed layer and the epitaxial layer which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.

3. The method of claim 1, further comprising the step of fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer.

4. The method of claim 3, wherein the step of fabricating at least one imaging component further includes the step of fabricating at least one of CMOS imaging components, charge-coupled device (CCD) components, photodiodes, avalanche photodiodes, and phototransistors.

5. The method of claim 2, further comprising the step of forming a plurality of alignment keys substantially overlying the epitaxial layer.

6. The method of claim 5, wherein the step of forming a plurality of alignment keys substantially overlying the epitaxial layer further includes the steps of:

printing key patterns on a top portion of the epitaxial layer,

etching the underlying epitaxial layer below the key patterns using a trench etch process until the etched away silicon is stopped by the underlying insulator layer; and

filling the opened trenches with an electrically insulating material.

7. The method of claim 2, wherein the step of forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well further comprises the steps of:

implanting dopant species about the outlined collecting well; and

thermally activating the dopants.

8. The method of claim 2, wherein the step of forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well further comprises the steps of:

forming trench outlines about the outlined collection well using photolithography on the surface of the epitaxial layer opposite the interface within an initial portion of the semiconductor substrate and the epitaxial layer;

trench etching the epitaxial layer within the trench outlines; and

filling the resulting trench with an electrically insulating material.

9. The method of claim 8, wherein the step of forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well further comprises the steps of:

opening a region about the filled trench;

implanting the opened region with dopants; and

thermally activating the dopants.

11. The method of claim 8, wherein the step of forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well further comprises the steps of:

forming trench outlines about the outlined collection well using photolithography on the surface of the epitaxial layer opposite the interface within an initial portion of the semiconductor substrate and the epitaxial layer;

trench etching the epitaxial layer within the trench;

partially filling the trench with an electrically insulating material; and

filling the remaining portion of the trench with an optically opaque material.

12. The method of claim 8, wherein the step of forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well further comprises the steps of:

forming trench outlines about the outlined collection well using photolithography on the surface of the epitaxial layer opposite the interface within an initial portion of the semiconductor substrate and the epitaxial layer;

trench etching the epitaxial layer within the trench outlines; and

filling the resulting trench with an optically opaque material.

13. A method for reducing crosstalk in a back-illuminated imager, comprising the steps of:

providing a substrate comprising

an insulator layer, and

a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer;

defining pixel regions in the seed layer, each pixel region outlining a collection well for collecting charge carriers;

depositing an electrically insulating layer substantially overlying the seed layer;

patterning the electrically insulating layer such that it forms a ring about location of the outlined collection well; and

growing an the epitaxial layer substantially about the seed layer and the ring using an epitaxial lateral overgrowth (ELO) technique.

14. The method of claim 13, wherein the step of patterning further comprises the steps of:

dry etching anisotropically part of the resulting electrically insulating ring; and

wet etching the remaining portion of the electrically insulating ring.

15. The method of claim 13, further comprising the step of diffusing one or more dopants into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile in the seed layer and the epitaxial layer which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.

16. The method of claim 15, further comprising the step of fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer.

17. A back-illuminated imaging device that minimizes crosstalk, comprising:

an insulator layer;

a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer;

an epitaxial layer formed substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers, and

one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer.

18. The device of claim 17, wherein the seed layer and the epitaxial layer have a net dopant concentration profile which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.

19. The device of claim 18, further comprising at least one imaging component at least partially overlying and extending into the epitaxial layer.

20. The device of claim 18, wherein the one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well comprises implanted dopants.

21. The device of claim 18, wherein the one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well comprises an etched trench filled with an electrically insulating material.

22. The device of claim 21, wherein the one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well further comprises a region opened about the filled trench that is implanted with dopants.

23. The device of claim 18, wherein the one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well further comprises an etched trench partially filled with an electrically insulating material and the remaining portion of the etched trench filled with an optically opaque material.

24. The device of claim 18, wherein the one of an electrical, optical, and electrical and optical barrier formed about the outlined collection well further comprises an etched trench filled with an optically opaque material.

25. A back-illuminated imaging device that minimizes crosstalk, comprising:

a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer, the seed layer having defined pixel regions, each pixel region outlining a collection well for collecting charge carriers;

an electrically insulating layer substantially overlying the seed layer, the electrically insulating layer being patterned such that it forms a ring about the outlined collecting well; and

an epitaxial layer grown substantially about the seed layer and the rings using an epitaxial lateral overgrowth (ELO) technique.

26. The device of claim 25, wherein the ring has a height of about 3 um.

27. The device of claim 25, wherein the seed layer and the epitaxial layer have a net dopant concentration profile which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.

28. The device of claim 27, further comprising at least one imaging component at least partially overlying and extending into the epitaxial layer.