NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME

• US 20090206393A1
• Filed: 02/18/2009
• Published: 08/20/2009
• Est. Priority Date: 02/19/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ariyoshi, Keiko, Muraoka, Koichi, Takashima, Akira, Kikuchi, Shoko
• Application Number:
  US12/388,040
• Publication Number:
  US 20090206393A1
• Time in Patent Office: Days
• US Class Current: 257/326
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating layer provided on the charge storage layer, and a control gate electrode provided on the block insulating layer. The charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized. The block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.

Claims

1. A nonvolatile memory element comprising:

a semiconductor region;

a source region and a drain region provided in the semiconductor region;

a tunnel insulating layer provided on the semiconductor region between the source region and the drain region;

a charge storage layer provided on the tunnel insulating layer;

a block insulating layer provided on the charge storage layer; and

a control gate electrode provided on the block insulating layer,

wherein the charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized, and

the block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.

2. The element according to claim 1, wherein the block insulating layer is entirely or partially crystallized.

3. The element according to claim 1, wherein the charge storage layer includes a first insulating layer which is provided in an interface to the tunnel insulating layer and is amorphous.

4. The element according to claim 3, wherein the first insulating layer includes silicon nitride.

5. A nonvolatile memory element comprising:

a semiconductor region;

a source region and a drain region provided in the semiconductor region;

a tunnel insulating layer provided on the semiconductor region between the source region and the drain region;

a charge storage layer including a first insulating layer which is provided on the tunnel insulating layer and is amorphous, and a second insulating layer which is granularly formed in the first insulating layer and crystallized;

a block insulating layer provided on the charge storage layer; and

a control gate electrode provided on the block insulating layer,

wherein the second insulating layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized, and the block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.

6. The element according to claim 5, wherein the second insulating layer is provided in an interface to the block insulating layer.

7. The element according to claim 5, wherein the first insulating layer includes silicon nitride.

8. A method of manufacturing a nonvolatile memory element, comprising:

forming a tunnel insulating layer on a semiconductor region;

forming a charge storage layer on the tunnel insulating layer;

crystallizing the charge storage layer by performing first annealing;

forming a block insulating layer on the charge storage layer;

forming a control gate electrode on the block insulating layer;

forming an impurity region in the semiconductor region by doping an impurity in the semiconductor region; and

activating the impurity region by performing second annealing.

9. The method according to claim 8, wherein the second annealing crystallizes the block insulating layer.

10. The method according to claim 8, wherein the charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized.

11. The method according to claim 8, wherein the block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.

12. The method according to claim 8, further comprising forming an amorphous insulating layer, after forming the tunnel insulating layer.

13. The method according to claim 12, wherein the insulating layer includes silicon nitride.