REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY SILICIDATION

• US 20090206404A1
• Filed: 02/15/2008
• Published: 08/20/2009
• Est. Priority Date: 02/15/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack T., Rakshit, Titash, Pillarisetty, Ravi
• Application Number:
  US12/032,588
• Publication Number:
  US 20090206404A1
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.

Claims

1. An apparatus comprising:

a semiconductor substrate;

a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a first surface, a second surface, and a third surface, the multi-gate fin further comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide; and

a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.

2. An apparatus according to claim 1 further comprising:

epitaxial growth coupled to the third surface of the multi-gate fin in the source and drain regions wherein the epitaxial growth comprises metal silicide, the spacer dielectric material being disposed to prevent epitaxial growth from being coupled to the first surface and the second surface, wherein the metal silicide of the multi-gate fin and the metal silicide of the epitaxial growth reduces external resistance (R_ext) of a multi-gate device incorporating the multi-gate fin.

3. An apparatus according to claim 2 wherein the metal silicide of the epitaxial growth comprises nickel and wherein the metal silicide of the multi-gate fin comprises nickel.

4. An apparatus according to claim 1 wherein the multi-gate fin comprises an aggregation of a dopant at an interface between the metal silicide of the multi-gate fin and the semiconductor substrate.

5. An apparatus according to claim 4 wherein the dopant is phosphorous and wherein the aggregation of phosphorous reduces external resistance (R_ext) of a multi-gate device incorporating the multi-gate fin.

6. An apparatus according to claim 1 wherein the semiconductor substrate is a bulk substrate comprising silicon, the bulk substrate being selected to allow deeper silicidation of the multi-gate fin in the source and drain regions than a silicon-on-insulator (SOI) substrate.

7. An apparatus according to claim 1 wherein the multi-gate fin is a tri-gate fin and wherein the first and second surfaces are substantially parallel to each other and wherein the third surface is substantially perpendicular to the first and second surfaces.

8. A method comprising:

forming at least one multi-gate fin on a semiconductor substrate, the multi-gate fin comprising a first surface, a second surface, and a third surface, the multi-gate fin further comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

depositing a spacer dielectric material to substantially cover the first surface and the second surface in the source and drain regions;

depositing epitaxial growth to the third surface in the source and drain regions;

depositing a metal to the epitaxial growth; and

thermally processing the metal to at least substantially silicidize the epitaxial growth and the multi-gate fin.

9. A method according to claim 8 wherein forming at least one multi-gate fin on a semiconductor substrate comprises forming at least one tri-gate fin on a bulk semiconductor substrate, wherein the bulk semiconductor substrate allows deeper silicidation of the tri-gate fin in the source and drain regions than a silicon-on-insulator (SOI) substrate.

10. A method according to claim 8 wherein depositing a spacer dielectric material prevents the deposition of epitaxial growth on the first surface and the second surface to allow a spacer-confined fully silicided (FUSI) process to substantially silicidize the multi-gate fin.

11. A method according to claim 8 wherein depositing epitaxial growth to the third surface in the source and drain regions comprises epitaxially growing silicon on the third surface wherein the third surface comprises silicon.

12. A method according to claim 8 wherein depositing a metal to the epitaxial growth comprises depositing nickel to the epitaxial growth, the method further comprising:

implanting the multi-gate fin prior to depositing a metal to control the depth of silicidation in the multi-gate fin.

13. A method according to claim 8 wherein thermally processing the metal to at least substantially silicidize the epitaxial growth and the multi-gate fin lowers the Schottky barrier of the multi-gate fin and reduces the external resistance (R_ext) of a multi-gate device that incorporates the multi-gate fin.

14. A method according to claim 8 wherein thermally processing the metal comprises annealing the metal wherein annealing the metal substantially silicidizes the epitaxial growth and substantially silicidizes the multi-gate fin and wherein annealing the metal plows a dopant in the multi-gate fin towards the semiconductor substrate.

15. A method according to claim 8 wherein thermally processing the metal plows a dopant comprising phosphorous in the multi-gate fin towards the semiconductor substrate, the phosphorous aggregating at an interface between the silicidized multi-gate fin and the semiconductor substrate to reduce external resistance (R_ext) in a multi-gate device or to reduce junction leakage in a multi-gate device, or combinations thereof.