MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE

• US 20090206406A1
• Filed: 02/15/2008
• Published: 08/20/2009
• Est. Priority Date: 02/15/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Kavalieros, Jack T., Rachmady, Willy
• Granted Patent: US 8,264,048 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

Claims

1. A method comprising:

forming a dummy gate pedestal having at least a first surface, a second surface, and a third surface wherein the first and second surfaces are substantially parallel to one another and wherein the third surface is substantially perpendicular to the first and second surfaces, the dummy gate pedestal comprising a dummy gate dielectric coupled to a gate region of a multi-gate fin, a first dummy gate material coupled to the dummy gate dielectric, and a second dummy gate material coupled to the first dummy gate material;

depositing a first spacer dielectric film to the first and second surfaces of the dummy gate pedestal;

depositing a second spacer dielectric film to the first spacer dielectric film;

selectively removing the second dummy gate material of the dummy gate pedestal to expose a portion of the first spacer dielectric film previously coupled to the second dummy gate material;

selectively removing the portion of the first spacer dielectric film previously coupled to the second dummy gate material;

selectively removing the first dummy gate material and the dummy gate dielectric to form a T-shaped trench in the gate region; and

forming a T-shaped gate stack in the T-shaped trench.

2. A method according to claim 1 wherein forming a dummy gate pedestal comprises:

depositing a dummy gate dielectric comprising oxide to the gate region of a multi-gate fin;

depositing a first dummy gate material comprising polysilicon to the dummy gate dielectric;

depositing a second dummy gate material comprising silicon germanium (SiGe) to the first dummy gate material; and

smoothing the second dummy gate material surface using a polish or etch process, or suitable combinations thereof.

3. A method according to claim 1 wherein depositing a first spacer dielectric film comprises depositing silicon nitride and wherein depositing a second spacer dielectric film comprises depositing carbon-doped silicon nitride.

4. A method according to claim 1 further comprising:

forming a source region and a drain region in the multi-gate fin after depositing a second spacer dielectric film and prior to selectively removing the second material of the dummy gate pedestal, wherein the gate region is disposed between the source and drain regions;

depositing an inter-layer dielectric (ILD) to the source region, drain region, and gate region of the multi-gate fin; and

polishing the ILD to expose the second dummy gate material of the dummy gate pedestal.

5. A method according to claim 1 wherein selectively removing the second dummy gate material of the dummy gate pedestal comprises etching the second dummy gate material using a wet etch comprising acetic acid, nitric acid, and hydrofluoric acid.

6. A method according to claim 1 wherein selectively removing the portion of the first spacer dielectric film previously coupled to the second dummy gate material comprises etching with phosphoric acid using the first dummy gate material as an etch mask.

7. A method according to claim 1 wherein selectively removing the first dummy gate material and the dummy gate dielectric comprises etching with trimethylammonium hydroxide (TMAH), ammonium hydroxide, potassium hydroxide, or suitable combinations thereof, to form a T-shaped trench wherein a cross-section of the trench contained between the first and second spacer dielectric films along the multi-gate fin has a substantially T-shaped structure to decrease gate region resistivity by facilitating gate electrode fill in the gate region.

8. A method according to claim 1 wherein forming a T-shaped gate stack in the T-shaped trench comprises:

depositing a high-k gate oxide to the gate region of the multi-gate fin;

depositing a workfunction metal to the high-k gate oxide to substantially fill the T-shaped trench.

9. A method according to claim 1 wherein selectively removing the second dummy gate material of the dummy gate pedestal, selectively removing the portion of the first spacer dielectric film previously coupled to the second dummy gate material, and selectively removing the first dummy gate material and the dummy gate dielectric comprise highly selective wet etch processes and do not comprise dry etch processes to reduce damage associated with dry etch processes.

10. A method according to claim 1 wherein forming a dummy gate pedestal coupled to a gate region of a multi-gate fin comprises forming a dummy gate pedestal coupled to a gate region of a tri-gate fin wherein the tri-gate fin is part of a transistor device having a gate length of about 22 nm or less.

11. An apparatus comprising:

a semiconductor substrate;

at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

a gate dielectric coupled to the gate region of the multi-gate fin;

a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness;

a first spacer dielectric coupled to a portion of the gate electrode having the first thickness; and

a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode wherein the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

12. An apparatus according to claim 11 wherein a cross-section of the gate electrode along the multi-gate fin has a substantially T-shaped structure to decrease gate electrode resistivity by increasing gate electrode fill in the gate region.

13. An apparatus according to claim 11 wherein the first spacer dielectric comprises silicon nitride and the second spacer dielectric comprises carbon-doped silicon nitride.

14. An apparatus according to claim 11 wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate dielectric comprises a high-k gate oxide, and the gate electrode comprises a workfunction metal.

15. An apparatus according to claim 11 wherein the multi-gate fin is a tri-gate fin that is part of a transistor having a gate length of about 22 nm or less.