DUAL METAL GATE STRUCTURES AND METHODS

• US 20090206416A1
• Filed: 02/19/2008
• Published: 08/20/2009
• Est. Priority Date: 02/19/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wong, Keith Kwong Hon, Cheng, Kangguo
• Application Number:
  US12/033,326
• Publication Number:
  US 20090206416A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Two dummy gate structures containing disposable material portions and metal portions, source and drain regions, and metal semiconductor alloy regions are formed on a semiconductor substrate. A dielectric material layer is deposited and planarized so that top surfaces of the two remaining dummy gate structures are substantially coplanar. A disposable material portion and a metal portion are removed from one dummy gate structure, while the other dummy gate structure is protected. Subsequently, another disposable material portion is removed from the other dummy gate structure. A second metal layer comprising a second metal is deposited and planarized to form two gate electrodes. One gate electrode has a gate dielectric abutting the first metal, while the other electrode has a gate electrode abutting the second metal. Both gate electrodes have substantially the same height since the two top surfaces of the gate electrodes are formed by the same planarization process.

Claims

1. A semiconductor structure comprising a first gate stack and a second gate stack located on a semiconductor substrate, wherein said first gate stack comprises a first gate dielectric vertically abutting said semiconductor substrate, a first metal portion vertically abutting said first gate dielectric and comprising a first metallic material, and a second metal portion vertically abutting said first metal portion and comprising a second metallic material which is different from said first metallic material, and wherein said second gate stack comprises a second gate dielectric vertically abutting said semiconductor substrate and a third metal portion vertically abutting said second gate dielectric and comprising said second metallic material.

2. The semiconductor structure of claim 1, wherein said first metal portion has a first thickness, said second metal portion has a second thickness, and said third metal portion has a third thickness, wherein the sum of said first thickness and said second thickness is substantially equal to said third thickness.

3. The semiconductor structure of claim 1, wherein a top surface of said second metal portion and a top surface of said third metal portion are substantially coplanar.

4. The semiconductor structure of claim 1, wherein said first gate dielectric and said second gate dielectric have a same composition.

5. The semiconductor structure of claim 4, wherein said first gate dielectric and said second gate dielectric comprise a material comprises one of HfO₂, ZrO₂, La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, Al₂ONy, TiO_xN_y, SrTiO_xN_y, LaAlO_xN_y, Y₂O_xN_y, a silicate thereof, an alloy thereof, and non-stoichiometric variants thereof, wherein each value of x is independently from about 0.5 to about 3 and each value of y is independently from 0 to about 2.

6. The semiconductor structure of claim 1, wherein said first metallic material has a work function between a valence band edge of a semiconductor material directly underneath said first gate dielectric and a mid-band-gap energy level of said semiconductor material.

7. The semiconductor structure of claim 6, wherein said semiconductor material is silicon, and wherein said first metallic material comprises one of Ru, Pd, Pt, Co, Ni, Ta_xAl_yN, W_xC_yN, a conductive metal oxide, and a combination thereof, wherein each value of x is independently from 0 to about 1 and each value of y is independently from 0 to about 1.

8. The semiconductor structure of claim 1, wherein said second metallic material has a work function between a conduction band edge of a semiconductor material directly underneath said second gate dielectric and a mid-band-gap energy level of said semiconductor material.

10. The semiconductor structure of claim 1, further comprising:

a first source region and a first drain region, each having a doping of a first conductivity type, abutting said first gate dielectric, located in said semiconductor substrate, and separated from each other; and

a second source region and a second drain region, each having a doping of a second conductivity type, abutting said second gate dielectric, located in said semiconductor substrate, and separated from each other, and separated from said first source region and said first drain region, wherein said second conductivity type is the opposite type of said first conductivity type.

11. The semiconductor structure of claim 10, further comprising:

a first source side metal semiconductor alloy vertically abutting said first source region;

a first drain side metal semiconductor alloy vertically abutting said first drain region;

a second source side metal semiconductor alloy vertically abutting said second source region; and

a second drain side metal semiconductor alloy vertically abutting said second drain region.

12. The semiconductor structure of claim 1, further comprising a dielectric material layer abutting said semiconductor substrate and having a top surface which is substantially coplanar with a top surface of said second metal portion and a top surface of said third metal portion.

9. The semiconductor structure of claim 9, wherein said semiconductor material is silicon, and wherein said second metallic material comprises one of Zr, W, Ta, Hf, Ti, Al, a metal carbide, a transition metal aluminide, and a combination thereof.

13. A method of forming a semiconductor structure comprising:

forming a first dummy gate structure and a second dummy gate structure on a semiconductor substrate, wherein said first dummy gate structure includes a stack of a first gate dielectric, a first metal portion comprising a first metallic material, and a first disposable material portion from bottom to top in that order and said second dummy gate structure includes a stack of a second gate dielectric, a second metal portion comprising said first metallic material, and a second disposable material portion from bottom to top in that order;

removing said second disposable material portion and said second metal portion, while preserving said second gate dielectric and said first disposable material portion;

removing said first disposable material portion, while preserving said first metal portion; and

forming a third metal portion directly on said second gate dielectric and a fourth metal portion directly on said first metal portion, wherein said third metal portion and said fourth metal portion comprise a second metallic material.

14. The method of claim 13, wherein said first metallic material and said second metallic material are different from each other.

15. The method of claim 13, further comprising:

forming a gate dielectric layer directly on said semiconductor substrate;

forming a first metal layer directly on said gate dielectric layer; and

forming a disposable material layer directly on said first metal layer, wherein said first and second gate dielectrics are formed by patterning of said gate dielectric layer, wherein said first and second metal portions are formed by patterning of said first metal layer, and wherein said first and second disposable material portions are formed by patterning of said disposable material layer.

16. The method of claim 13, further comprising:

depositing a dielectric material layer over said first dummy gate structure, said second dummy gate structure, and said semiconductor substrate; and

planarizing said dielectric material layer, wherein a top surface of said first dummy gate structure and a top surface of said second dummy gate structure are substantially coplanar with a top surface of said dielectric material layer after said planarizing.

17. The method of claim 16, wherein said first dummy gate structure includes a first dielectric cap and said second dummy gate structure includes a second dielectric cap, and wherein said method further comprises removing said first and second dielectric cap during said planarizing.

18. The method of claim 13, further comprising:

forming a first source region and a first drain region prior to removal of said first disposable material portion and said first metal portion, wherein each of said first source region and said first drain region has a doping of a first conductivity type, abuts said first gate dielectric, is located in said semiconductor substrate, and is separated from each other; and

forming a second source region and a second drain region prior to said removal of said first disposable material portion and said first metal portion, wherein each of said second source region and said second drain region has a doping of a second conductivity type, abuts said second gate dielectric, is located in said semiconductor substrate, and is separated from each other, and wherein said second conductivity type is the opposite type of said first conductivity type.

19. The method of claim 18, further comprising forming a first source side metal semiconductor alloy, a first drain side metal semiconductor alloy, a second source side metal semiconductor alloy, and a second drain side metal semiconductor alloy prior to said removal of said first disposable material portion and said first metal portion, wherein said first source side metal semiconductor alloy is formed directly on said first source region, said first drain side metal semiconductor alloy is formed directly on said first drain region, said second source side metal semiconductor alloy is formed directly on said second source region, and said second drain side metal semiconductor alloy is formed directly on said second drain region.

20. The method of claim 16, further comprising:

depositing a second metal layer on said second gate dielectric and said first metal portion; and

removing portions of said second metal layer above said dielectric material layer, wherein said third metal portion and said fourth metal portions are remaining portions of said second metal layer after said removing.