SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRING BOARD

• US 20090206470A1
• Filed: 02/17/2009
• Published: 08/20/2009
• Est. Priority Date: 02/18/2008
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Miyasaka, Toshiji, Horiuchi, Akio
• Granted Patent: US 8,217,509 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]

Abstract

In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Claims

1. A semiconductor device manufacturing method comprising:

a semiconductor chip mounting step of mounting a semiconductor chip on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided;

an insulating layer forming step of forming an insulating layer so as to cover the side of the semiconductor chip on which the terminal electrodes are provided;

a through electrode forming step of forming through electrodes which connect to the terminal electrodes and pierce the insulating layer;

a metal wiring forming step of forming metal wiring connecting to the through electrodes on the insulating layer; and

an external terminal electrode forming step of forming external terminal electrodes for connecting the metal wiring to the outside on the metal wiring,

wherein spacing between the adjacent external terminal electrodes is larger than spacing between the adjacent terminal electrodes.

2. The semiconductor device manufacturing method as claimed in claim 1 wherein said semiconductor chip mounting step is to adhere the semiconductor chip to the support board with an adhesive.

3. The semiconductor device manufacturing method as claimed in claim 1 wherein the support board is a copper plate or a kovar plate.

4. The semiconductor device manufacturing method as claimed in claim 1 wherein the insulating layer is an epoxy-based resin or a polyimide-based resin.

5. The semiconductor device manufacturing method as claimed in claim 1 wherein said semiconductor chip mounting step comprises:

a metal film forming step of forming a first metal film on the support board and a second metal film on the first metal film;

a fit hole forming step of forming the second metal film with a fit hole to fit the semiconductor chip; and

a fit and adhesion step of fitting the semiconductor chip into the fit hole and adhering the semiconductor chip to the fit hole with an adhesive.

6. The semiconductor device manufacturing method as claimed in claim 5 wherein the fit hole forming step is to deposit a dry film resist on the second metal film, expose and develop the dry film resist to form a resist pattern corresponding to the fit hole, and etch the second metal film formed with the resist pattern.

7. The semiconductor device manufacturing method as claimed in claim 5 wherein the support board is any one of a copper plate, a kovar plate, a nickel plate, or a glass epoxy board.

8. The semiconductor device manufacturing method as claimed in claim 5 wherein the first metal film contains gold.

9. The semiconductor device manufacturing method as claimed in claim 5 wherein the second metal film is copper.

10. The semiconductor device manufacturing method as claimed in claim 1 wherein said semiconductor chip mounting step comprises:

a fit hole forming step of forming the support board with a fit hole to fit the semiconductor chip; and

a fit and adhesion step of fitting the semiconductor chip into the fit hole and adhering the semiconductor chip to the fit hole with an adhesive.

11. The semiconductor device manufacturing method as claimed in claim 10 wherein the fit hole forming step is to deposit a dry film resist on the support board, expose and develop the dry film resist to form a resist pattern corresponding to the fit hole, and etch the support board formed with the resist pattern.

12. The semiconductor device manufacturing method as claimed in claim 10 wherein the support board is a copper plate or a kovar plate.

13. A semiconductor device comprising:

a semiconductor chip;

a support board which supports said semiconductor chip;

a plurality of terminal electrodes provided on semiconductor chip;

a plurality of external terminal electrodes which connect said terminal electrodes to the outside; and

a fan out section which electrically connects said terminal electrodes and said external terminal electrodes, said fan out section including

an insulating layer which covers said terminal electrodes;

through electrodes which connect to said terminal electrodes and pierce the insulating layer; and

metal wirings which connects to the through electrodes and are formed on the insulating layer,

wherein spacing between said adjacent external terminal electrodes is larger than spacing between said adjacent terminal electrodes.

14. The semiconductor device as claimed in claim 13 wherein said semiconductor chip is adhered to said support board with an adhesive and a side of said semiconductor chip on which said terminal electrodes are provided is covered with the insulating layer.

15. The semiconductor device as claimed in claim 13 further comprising:

a first metal film provided on said support board; and

a second metal film provided on said support board through the first metal film, said the second metal film having a fit hole to fit said semiconductor chip,

wherein said semiconductor chip is fitted into the fit hole so that the side of the semiconductor chip on which said terminal electrodes are provided is exposed, and is adhered to the fit hole with an adhesive.

16. The semiconductor device as claimed in claim 13 wherein said support board is formed with a fit hole to fit said semiconductor chip, and wherein

said semiconductor chip is fitted into the fit hole so that the side of the semiconductor chip on which said terminal electrodes are provided is exposed, and is adhered to the fit hole with an adhesive.

17. The semiconductor device as claimed in claim 13 wherein a plurality of said semiconductor chips are mounted.

18. A wiring board comprising;

a semiconductor device as claimed in claim 13;

a wiring board substrate on which said semiconductor device is mounted; and

wiring board terminal electrodes provided on the wiring board substrate in a one-to-one correspondence with the external terminal electrodes,

wherein the external terminal electrodes and the wiring board terminal electrodes are electrically connected.