Edge Termination with Improved Breakdown Voltage

• US 20090206913A1
• Filed: 02/09/2009
• Published: 08/20/2009
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Su, Shih-Tzung
• Granted Patent: US 7,923,804 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.

Claims

1. A semiconductor device, comprising:

one or more active device segments;

an edge termination structure, surrounding one or more of said active device segments; and

multiple trench field plates, successively surrounding said edge termination and each other;

wherein ones of said field plates are embedded in respective trenches, and wherein respective concentrations of a compensating dopant lie beneath said trenches.

2. The device of claim 1, wherein an additional field plate, which is not embedded in a trench, also surrounds one or more of said trench field plates.

3. The device of claim 1, wherein said active device segments include vertical field-effect transistors.

4. The device of claim 1, wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder.

5. The device of claim 1, wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder;

and wherein said recessed field plates in said active device segments have the same characteristics as one or more of said trench field plates.

6. The device of claim 1, wherein multiple ones of said trench field plates are electrically floating.

7. The device of claim 1, wherein said respective concentrations of a compensating dopant, under multiple ones of said trench field plates, are heavy enough to invert the conductivity type of material thereunder.

8. The device of claim 1, wherein said respective concentrations of a compensating dopant, under multiple ones of said trench field plates, are outdiffused far enough to mutually overlap.

9. The device of claim 1, further comprising at least one non-trench field plate inboard of said trench field plates.

10. The device of claim 1, wherein said active device segments include a body junction which extends into some, but not all, of said termination.

11. The device of claim 1, wherein said active device segments and said termination are constructed in epitaxial semiconductor material.

12. The device of claim 1, further comprising a transition zone, between the active device segments and said edge termination structure.

13. (canceled)

14. A semiconductor device, comprising:

one or more active device segments having a body junction therein;

an edge termination structure, surrounding one or more of said active device segments, and including a sandwich structure having back-to-back junctions, of which one is approximately coplanar with said body junction; and

one or more field plates, capacitively coupled to said edge termination structure.

15. The device of claim 14, wherein said sandwich structure includes a p-type middle layer between n-type layers.

16. The device of claim 14, wherein said body junction is less than 0.5 micron deep.

17. The device of claim 14, comprising a plurality of said field plates.

18-36. -36. (canceled)

37. A method of operating a power semiconductor device, comprising the actions of:

a) providing a desired current characteristic using one or more active device segments;

while also simultaneously

b) avoiding edge breakdown by using an edge termination structure, surrounding one or more of said active device segments, and multiple trench field plates, successively surrounding said edge termination and each other;

wherein ones of said field plates are embedded in respective trenches, and wherein respective concentrations of a compensating dopant lie beneath said trenches.

38. The method of claim 37, wherein an additional field plate, which is not embedded in a trench, also surrounds one or more of said trench field plates.

39. The method of claim 37, wherein said active device segments include vertical field-effect transistors.

40. The method of claim 37, wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder.

41-67. -67. (canceled)