SEMICONDUCTOR DEVICE AND CELL PLATE VOLTAGE GENERATING APPARATUS THEREOF

• US 20090206918A1
• Filed: 09/09/2008
• Published: 08/20/2009
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: JUNG, Ho Don
• Granted Patent: US 8,000,160 B2
• Time in Patent Office: Days
• US Class Current: 327/538
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor device includes a monitor voltage transfer unit and a voltage generating unit. The monitor voltage transfer unit selects one of a plurality of internal voltages including a cell plate voltage in accordance with a test mode to output it to a voltage monitor pad or outputs an external voltage supplied from the voltage monitor pad as a first pre cell plate voltage. The voltage generating unit generates the cell plate voltage using any one of the first pre cell plate voltage and a second pre cell plate voltage generated within itself in accordance with the test mode. The semiconductor device can generate a pre cell plate voltage at the desired level.

Claims

1. A semiconductor device, comprising:

a monitor voltage transfer unit outputting an internal voltage including at least a cell plate voltage to a voltage monitor pad in accordance with a test mode, or supplying an external voltage from the voltage monitor pad and outputting a first pre cell plate voltage in accordance with the test mode; and

a voltage generating unit generating the pre cell plate voltage by using either the first pre cell plate voltage or a second pre cell plate voltage generated within the voltage generating unit in accordance with the test mode.

2. The semiconductor device as set forth in claim 1, wherein the monitor voltage selecting unit comprises:

a decoding signal generating unit combining an enable signal, with a test mode signal to generate a first and a second decoding signal which determines the test mode; and

a transfer unit transferring the internal voltage to the voltage monitor pad in response to the first decoding signal, or transferring the external voltage supplied from the monitor pad as the second pre cell plate voltage to the voltage generating unit in response to the second decoding signal.

3. The semiconductor device as set forth in claim 2, wherein the decoding signal generating unit comprises:

a decoding control signal generating unit combining the enable signal with the test mode signal to generate decoding control signals; and

a decoder combining the decoding control signals to output the first and the second decoding signal.

4. The semiconductor device as set forth in claim 2, wherein the voltage generating unit comprises:

a pre cell plate voltage generating unit selectively generating the second pre cell plate voltage in response to the second decoding signal; and

a driver amplifying and driving the first pre cell plate voltage or the second pre cell plate voltage to generate the cell plate voltage.

5. The semiconductor device as set forth in claim 4, wherein the pre cell plate voltage generating unit generates the second pre cell plate voltage by selectively distributing a core voltage in response to the second decoding signal.

6. The semiconductor device as set forth in claim 5, wherein the pre cell plate voltage generating unit comprises:

a first switching unit switching a supply of the core voltage in response to the second decoding signal;

a second switching unit switching a supply of a ground voltage in response to the second decoding signal;

an output node formed between the first switching unit and the second switching unit to output the second pre cell plate voltage, and the first pre cell plate voltage is selectively supplied to the output node via the transfer unit.

7. The semiconductor device as set forth in claim 1, wherein the external voltage is supplied from the outside to the voltage monitor pad to control a level of the cell plate voltage at a desired level according to a test specification.

8. A semiconductor device, comprising:

a decoding signal generating unit combining an enable signal with a test mode signal to generate a decoding signal;

a voltage providing unit providing an internal voltage including at least a cell plate voltage or a pre cell plate voltage in response to the decoding signal;

a voltage monitor pad receiving the internal voltage provided to the voltage providing unit and an external voltage to use as the pre cell plate voltage; and

a driver driving the pre cell plate voltage to generate the cell plate voltage.

9. The semiconductor device as set forth in claim 8, wherein the voltage providing unit providing the pre cell plate voltage generated within itself in response to the decoding signal, or providing the pre cell plate voltage corresponding to the external voltage in response to the decoding signal.

10. The semiconductor device as set forth in claim 9, wherein the voltage providing unit comprises:

a pre cell plate voltage generating unit selectively generating the pre cell plate voltage in response to the decoding signal and outputting the pre cell plate voltage to the driver; and

a transfer unit transferring the internal voltage to the voltage monitor pad in response to the decoding signal, or transferring the external voltage to an output terminal of the voltage generating unit in response to the decoding signal.

11. The semiconductor device as set forth in claim 10, wherein the pre cell plate voltage generating unit generates the pre cell plate voltage by selectively distributing a core voltage in response to the decoding signal.

12. The semiconductor device as set forth in claim 11, wherein the pre cell plate voltage generating unit comprises a first switching unit switching a supply of the core voltage in response to the decoding signal and a second switching unit switching a supply of a ground voltage in response to the decoding signal, the output terminal is formed between the first and second switching units to output the pre cell plate voltage, and the external voltage is selectively supplied to the output terminal via the transfer unit.

13. The semiconductor device as set forth in claim 8, wherein the external voltage is supplied from the outside to the voltage monitor pad to control a level of the cell plate voltage at a desired level according to a test specification.

14. A cell plate voltage generating device, comprising:

a pre cell plate voltage generating unit that receives a test signal, wherein;

when the test signal is disabled, a pre cell plate voltage generating unit receives an internal voltage and generates a pre cell plate voltage, and

when the test signal is enabled, the pre cell plate voltage generating unit generates the pre cell plate voltage corresponding to the external voltage supplied via a voltage pad; and

a driver driving the pre cell plate voltage to generate a cell plate voltage.

15. The cell plate voltage generating device as set forth in claim 14, further comprising:

a transfer gate connecting an output node of the pre cell plate voltage generating unit to the voltage pad when the test signal is enabled.

16. The cell plate voltage generating apparatus as set forth in claim 14, wherein the pre cell plate voltage generating unit comprises:

a voltage dividing unit dividing the internal voltage; and

a control unit causing the voltage dividing unit to float the internal voltage when the test signal is enabled.