CHARGE PUMP-BASED FREQUENCY MODULATOR

• US 20090206941A1
• Filed: 02/12/2009
• Published: 08/20/2009
• Est. Priority Date: 02/19/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chang, Hsiu-Ming, Wang, Ping-Ying
• Granted Patent: US 7,893,788 B2
• Time in Patent Office: Days
• US Class Current: 332/119
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/0975 applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock
• CPC Class Codes: H03C 3/20 the element being a voltage-dependent capacitor
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data.

Claims

1. A charge pump-based frequency modulator, comprising:

an analog phase correction path comprising a varactor coupled to an output of the charge pump-based frequency modulator; and

a charge pump coupled to a node between the varactor and the output and receiving a signal containing the modulated data.

2. The charge pump-based frequency modulator as claimed in claim 1, further comprising a high pass filter coupled between the node and the output.

3. The charge pump-based frequency modulator as claimed in claim 2, wherein the charge pump is a programmable charge pump circuit.

4. The charge pump-based frequency modulator as claimed in claim 3, wherein the programmable charge pump circuit comprises a logic circuit receiving the signal containing the modulated data and a plurality of pull-up current sources and a plurality of pull-down current sources selectively coupled to the node according to control signals from the logic circuit.

5. The charge pump-based frequency modulator as claimed in claim 4, wherein the logic circuit comprises a first AND gate receiving a most significant bit and the remaining bits of the signal containing the modulated data and a second AND gate receiving an inverse of the most significant bit and the remaining bits of the signal containing the modulated data, wherein outputs of the first and second AND gate are used to control one of each and remaining pull-up current sources and pull-down current sources.

6. The charge pump-based frequency modulator as claimed in claim 5, wherein the signal containing the modulated date is normalized by an multiplier before being received by the logic circuit.

7. The charge pump-based frequency modulator as claimed in claim 1, further comprising a frequency divider coupled between the output and input of the charge pump-based frequency modulator and a sigma delta modulator receiving the signal containing the modulated data.

8. The charge pump-based frequency modulator as claimed in claim 1, further comprising a digital frequency correction path comprising a digital integral path circuit receiving the signal containing the modulated data.