High Voltage Isolation Semiconductor Capacitor Digital Communication Device and Corresponding Package

• US 20090206958A1
• Filed: 02/15/2008
• Published: 08/20/2009
• Est. Priority Date: 02/15/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies ECBU IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Lee, Kah Wang, Chow, Fun Kok, Ng, Gek-Yong
• Granted Patent: US 7,741,935 B2
• Time in Patent Office: Days
• US Class Current: 333/247
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

According to one embodiment, there is provided a semiconductor digital communication device comprising communication drive and sense electrodes formed in a single plane, where the electrodes have relatively high sidewalls. The relatively high sidewalls permit low electrical field densities to be obtained in the sense and drive electrodes during operation, and further permit very high breakdown voltages to be obtained between the electrodes, and between the drive electrode and an underlying ground plane substrate. The device effects communications between drive and receive circuits through the drive and sense electrodes by capacitive means, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The device may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes.

Claims

1. A high voltage isolation semiconductor digital communication device, comprising:

at least one communication drive electrode comprising a drive input and opposing substantially vertical sidewalls having a height of about T_n, the drive electrode further being formed of a first electrically conductive metal, metal alloy or metal mixture;

at least one communication sense electrode comprising a sense output and opposing substantially vertical sidewalls having the height of about T_n, the sense electrode being formed of a second electrically conductive metal, metal alloy or metal mixture;

an electrically conductive ground plane substrate spaced apart from the drive and sense electrodes by an electrically insulative layer having a thickness d;

a drive circuit operably coupled to the drive input and configured to transmit a communication drive signal therethrough, and

a receive circuit operably coupled to the sense output and configured to receive the communication drive signal transmitted between the sense and drive electrodes;

wherein the drive and sense communication electrodes are disposed substantially in a single plane and are operably configured and associated in respect of one another to effect the transfer of digital communication signals therebetween by capacitive means, the sidewall heights T_n exceed about 1 micron thereby to decrease electrical field densities associated therewith, the sense and drive electrodes are separated by an inter-electrode spacing T_d exceeding about 1 micron, the inter-electrode spacing T_d is greater than or equal to the thickness d, and a first breakdown voltage between the drive electrode and the sense electrode exceeds about 2,000 volts RMS when applied over a time period of about one minute.

2. The device of claim 1, wherein the first breakdown voltage exceeds about 2,500 volts RMS when applied over a time period of about one minute.

3. The device of claim 1, wherein the first breakdown voltage exceeds about 3,000 volts RMS when applied over a time period of about one minute.

4. The device of claim 1, wherein the first breakdown voltage is greater than or equal to a second breakdown voltage between the drive electrode and the ground plane substrate.

5. The device of claim 1, wherein the inter-electrode spacing T_d is about 1.5 times greater than the thickness d of the electrically insulative layer.

6. The device of claim 1, wherein the inter-electrode spacing T_d is about 2.0 times greater than the thickness d of the electrically insulative layer.

7. The device of claim 1, wherein the sidewall heights T_n range between about 1 micron and about 6 microns.

8. The device of claim 1, wherein the sidewall heights T_n range between about 1 micron and about 3 microns.

9. The device of claim 1, wherein the inter-electrode spacing T_d ranges between about 1 micron and about 15 microns.

10. The device of claim 1, wherein the first and second metals, metal alloys or metal combinations are substantially the same.

11. The device of claim 1, wherein the first and second metals, metal alloys or metal combinations comprise one or more of gold, silver, copper, tungsten, tin, aluminium, and aluminium-copper.

12. The device of claim 1, wherein the electrically insulative layer comprises one or more of a semiconductor dielectric material, silicon oxide, silicon nitride and thick oxide.

13. The device of claim 1, wherein the electrically conductive ground plane substrate is formed of a semiconductor dielectric material or silicon.

14. The device of claim 1, wherein the sense and drive electrodes are separated by at least one electrically insulative material disposed therebetween.

15. The device of claim 14, wherein the electrically insulative material comprises one or more of a semiconductor dielectric material, silicon oxide, silicon nitride and thick oxide.

16. The device of claim 1, wherein the at least one drive electrode comprises a plurality of drive electrodes.

17. The device of claim 16, wherein the plurality of drive electrodes are configured to transmit differential signals therethrough.

18. The device of claim 1, wherein the at least one sense electrode comprises a plurality of sense electrodes.

19. The device of claim 18, wherein the plurality of sense electrodes are configured to receive differential signals therethrough.

20. The device of claim 1, wherein the drive and sense electrodes are interleaved with one another.

21. The device of claim 1, wherein the drive and sense electrodes are spirally wound.

22. The device of claim 1, wherein the electric field densities do not exceed about 400 volts/micron when a voltage placed across the sense and drive electrode ranges between about 2,000 volts RMS and about 3,000 volts RMS.

23. The device of claim 1, wherein the drive and sense electrodes, the electrically insulative layer, and the ground plane substrate are fabricated using one or more of a CMOS process, a Bipolar-CMOS process, and a combined Bipolar-CMOS-DMOS (BCD) process.

24. The device of claim 1, wherein the device is encapsulated at least partially in polyimide or plastic.

25. The device of claim 1, wherein the drive and receive circuits are incorporated into an integrated circuit.

26. The device of claim 1, wherein the receive circuit further comprises a common mode rejection (CMR) circuit.

27. The device of claim 1, wherein the device is configured to transfer data between the drive and receive circuits at a rate of up to about 300 Megabits per second.

28. A method of making a high voltage isolation semiconductor digital communication device, comprising:

providing at least one communication drive electrode comprising a drive input and opposing substantially vertical sidewalls having a height of about T_n, the drive electrode further being formed of a first electrically conductive metal, metal alloy or metal mixture;

providing at least one communication sense electrode comprising a sense output and opposing substantially vertical sidewalls having a height of about T_n, the sense electrode being formed of a second electrically conductive metal, metal alloy or metal mixture;

providing an electrically conductive ground plane substrate spaced apart from the drive and sense electrodes by an electrically insulative layer having a thickness d;

providing a drive circuit operably coupled to the drive input and configured is to transmit a communication drive signal therethrough, and

providing a receive circuit operably coupled to the sense output and configured to receive the communication drive signal transmitted between the sense and drive electrodes;

wherein the drive and sense communication electrodes are disposed substantially in a single plane and are operably configured and associated in respect of one another to effect the transfer of digital communication signals therebetween by capacitive means, the sidewall heights T_n exceed about 1 micron thereby to decrease electrical field densities associated therewith, the sense and drive electrodes are separated by an inter-electrode spacing T_d exceeding about 1 micron, the inter-electrode spacing T_d is greater than or equal to the thickness d, and a first breakdown voltage between the drive electrode and the sense electrode exceeds about 2,000 volts RMS when applied over a time period of about one minute.

29. The method of claim 28, wherein the first breakdown voltage exceeds at least one of about 2,500 volts RMS when applied over a time period of about one minute, and about 3,000 volts RMS when applied over a time period of about one minute.

30. The method of claim 28, wherein the first breakdown voltage is greater than or equal to a second breakdown voltage between the drive electrode and the ground plane substrate.

31. The method of claim 28, wherein the inter-electrode spacing T_d is at least one of about 1.5 times greater than the thickness d of the electrically insulative layer and about 2.0 times greater than the thickness d of the electrically insulative layer.

32. The method of claim 28, wherein the sidewall height T_n ranges between about 1 micron and about 6 microns, or between about 1 micron and about 3 microns.

33. The method of claim 32, wherein the inter-electrode spacing T_d ranges between about 1 micron and about 15 microns.