PROGRAM METHOD OF FLASH MEMORY DEVICE

• US 20090207660A1
• Filed: 04/16/2009
• Published: 08/20/2009
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Min Kyu, Kim, Hyung Seok, Noh, Keum Hwan, Hwang, Kyung Pil, Kim, Sook Kyung, Kim, Ju In, Joo, Seok Jin
• Granted Patent: US 7,990,771 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Claims

1. A program method of a flash memory device including a plurality of MLCs that share word lines and bit lines, the program method comprising the steps of:

selecting one of the word lines;

first programming the MLCs connected to the selected word line by applying a first program voltage that gradually rises from a start program voltage at the ratio of a first step voltage to the selected word line; and

first programming the MLCs connected to the selected word line by applying a second program voltage that gradually rises from the first program voltage, which has finally risen in the first program step, at the ratio of a second step voltage.

2. The program method as claimed in claim 1, wherein the second step voltage is higher than the first step voltage.

3. The program method as claimed in claim 1, wherein the first program step includes:

a first supply step of supplying the first program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading first data from the MLCs connected to the selected word line by applying a first verify voltage to the selected word line;

a step of generating first verify data based on the first data;

a first determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the first verify data; and

a step of repeating the first supply step to the first determination step until the program of the MLCs connected to the selected word line is completed,

wherein the first program voltage, which is applied to the selected word line in the first supply step performed after the first determination step, is the first voltage higher than the first program voltage, which is applied to the selected word line in the first supply step executed prior to the first determination step.

4. The program method as claimed in claim 3, wherein the second program step includes:

a second supply step of supplying the second program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading second data from the MLCs connected to the selected word line by applying a second verify voltage to the selected word line;

a step of generating second verify data based on the second data;

a second determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the second verify data; and

a step of repeating the second supply step to the second determination step until the program of the MLCs connected to the selected word line is completed,

wherein the second program voltage, which is applied to the selected word line in the second supply step performed after the second determination step, is the second step voltage higher than the second program voltage, which is applied to the selected word line in the second supply step executed prior to the second determination step.

5. The program method as claimed in claim 4, further comprising the step of third programming the MLCs connected to the selected word line by applying the start program voltage that gradually rises from a start voltage at the ratio of the first step voltage to the selected word line, between the selection step and the first program step,

wherein the third program step includes:

a third supply step of supplying the start program voltage to the selected word line so that the MLCs connected to the selected word line are programmed;

a step of reading third data from the MLCs connected to the selected word line by applying a third verify voltage to the selected word line;

a step of generating third verify data based on the third data;

a third determination step of determining whether the program of the MLCs connected to the selected word line has been completed according to logic values of the third verify data; and

a step of repeating the third supply step to the third determination step until the program of the MLCs connected to the selected word line is completed,

wherein the start program voltage, which is applied to the selected word line in the third supply step performed after the third determination step, is the first step voltage higher than the start program voltage, which is applied to the selected word line in the third supply step executed prior to the third determination step.

6. The program method as claimed in claim 5, wherein the second verify voltage is higher than the first verify voltage and the first verify voltage is higher than the third verify voltage.