Multi-Transistor Non-Volatile Memory Element

• US 20090207662A1
• Filed: 02/20/2008
• Published: 08/20/2009
• Est. Priority Date: 02/20/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chun Jung, Wang, Shih Wei
• Granted Patent: US 8,008,702 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Claims

1. A multi-transistor element, comprising:

a substrate;

a first floating gate stack disposed on the substrate;

a second floating gate stack disposed on the substrate and coupled to the first floating gate stack; and

a first active region disposed in the substrate and coupled to the first and second floating gate stacks.

2. The multi-transistor element of claim 1, further comprising:

a second active region disposed in the substrate and coupled to the first floating gate stack; and

a third active region disposed in the substrate and coupled to the second floating gate stack.

3. The multi-transistor element of claim 1, further comprising:

a first control gate stack disposed on the first and second floating gate stacks.

4. The multi-transistor element of claim 1, further comprising:

an erase gate stack disposed on the substrate and coupled to the first and second floating gate stacks.

5. The multi-transistor element of claim 4, wherein the erase gate stack is coupled to at least one other element and the first active region is coupled to at least one other element

6. The multi-transistor element of claim 1, further comprising:

a first wordline gate stack coupled to the first floating gate stack; and

a second wordline gate stack coupled to the second floating gate stack.

7. The multi-transistor element of claim 1, wherein the second active region is coupled to a first bitline and the third active region is coupled to a second bitline.

8. The multi-transistor element of claim 7, wherein the first bitline is a read-bitline and wherein the second bitline is a program-bitline.

9. A method for operating a multi-transistor element comprising a first floating gate stack disposed on a substrate and a second floating gate stack disposed on the substrate and coupled to the first floating gate stack, first and second active regions, a program-bitline connected to the first region, and a read-bitline corresponding to the program-bitline and connected to the second active region, the method comprising programming the multi-transistor element using the program-bitline, wherein during the programming, the read-bitline is inhibited.

10. The method of claim 9, wherein the programming is done by source-side hot electron injection.

11. The method of claim 9, wherein the read-bitline is inhibited by being coupled to VCC.

12. The method of claim 9, further comprising:

reading using the read-bitline, wherein during the reading the program-bitline is inhibited.

13. The method of claim 12, wherein the program-bitline is inhibited by being coupled to ground.

14. A method for manufacturing a multi-transistor element, the method comprising:

forming a shallow trench isolation structure in a substrate; and

forming two coupled floating gate stacks adjacent the shallow trench isolation structure, wherein the two coupled floating gate stacks remain coupled.

15. The method of claim 14, further comprising:

forming a control gate stack adjacent the two coupled floating gate stacks.

16. The method of claim 14, further comprising:

forming a common source adjacent the two coupled floating gate stacks.

17. The method of claim 15, further comprising:

forming a wordline gate stack adjacent the two coupled floating gate stacks and the control gate stack; and

forming an erase gate stack adjacent the two coupled floating gate stacks and the control gate stack.

18. The method of claim 17, further comprising:

forming a first drain adjacent the wordline gate stack; and

forming a second drain adjacent the wordline gate stack.

19. The method of claim 18, further comprising:

coupling the first drain region to a first bitline; and

coupling the second drain region to a second bitline.

20. The method of claim 19, wherein the first bitline is operable to be used to program the two coupled floating gates and the second bitline is operable to be used to read from the two coupled floating gates.

21. The method of claim 16, wherein the two coupled floating gate stacks include a wordline gate stack side and a common source side, and wherein the two coupled floating gate stacks are coupled on the common source side and are separated on the wordline gate stack side.

22. The method of claim 14, wherein floating gates of the two coupled floating gate stacks are formed by chemical mechanical polishing.

23. The method of claim 14, wherein floating gates of the two coupled floating gate stacks are self-aligned gates.

24. The method of claim 14, wherein the two coupled floating gate stacks are formed by a patterning and etching process.