Flash Memory Device for Variably Controlling Program Voltage and Method of Programming the Same
First Claim
1. A method of programming a flash memory device, the method comprising:
- setting increments of program voltages according to one or more data states expressed as one or more threshold voltage distributions of multi-level memory cells;
generating an Increment Step Pulse Programming (ISPP) clock signal in response to program pass/fail information, the ISPP clock signal corresponding to a loop clock signal and to the increments of the program voltages;
generating a default level enable signal by performing a first counting operation that counts up to the increments of the program voltages, in response to the loop clock signal;
generating an additional level enable signal by performing a second counting operation that counts up to the increments of the program voltages, in response to the ISPP clock signal;
increasing the program voltage by 1 increment, in response to the default level enable signal; and
increasing the program voltage by 2 increments, in response to the additional level enable signal.
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Accused Products
Abstract
Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.
15 Citations
20 Claims
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1. A method of programming a flash memory device, the method comprising:
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setting increments of program voltages according to one or more data states expressed as one or more threshold voltage distributions of multi-level memory cells; generating an Increment Step Pulse Programming (ISPP) clock signal in response to program pass/fail information, the ISPP clock signal corresponding to a loop clock signal and to the increments of the program voltages; generating a default level enable signal by performing a first counting operation that counts up to the increments of the program voltages, in response to the loop clock signal; generating an additional level enable signal by performing a second counting operation that counts up to the increments of the program voltages, in response to the ISPP clock signal; increasing the program voltage by 1 increment, in response to the default level enable signal; and increasing the program voltage by 2 increments, in response to the additional level enable signal. - View Dependent Claims (2, 3, 4)
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5. A flash memory device comprising:
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a program control logic unit generating a loop clock signal and an Increment Step Pulse Programming (ISPP) information signal, in response to program pass/fail information; an ISPP control logic unit generating a default level enable signal and an additional level enable signal, in response to the loop clock signal and the ISPP information signal; a program voltage regulator variably increasing a program voltage, distributing the program voltage and comparing it to a reference voltage, and generating a pumping clock signal according to the result of the comparison, in response to the default level enable signal and the additional level enable signal; and a charge pump unit generating the program voltage, in response to the pumping clock signal. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A flash memory device comprising:
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a program control logic unit generating a loop clock signal, an Increment Step Pulse Programming (ISPP) information signal, a discharge enable signal, and a regulator enable signal, in response to program pass/fail information; an ISPP control logic unit generating a default level enable signal and an additional level enable signal, in response to the loop clock signal and the ISPP information signal; a program voltage regulator variably increasing a program voltage, distributing the program voltage, generating a first voltage by distributing the program voltage, comparing the first voltage with a reference voltage, and generating a pumping clock signal, in response to the discharge enable signal, the default level enable signal, the additional level enable signal, and the regulator enable signal; and a charge pump unit generating the program voltage, in response to the pumping clock signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification