Clock recovery circuit

• US 20090207957A1
• Filed: 01/29/2009
• Published: 08/20/2009
• Est. Priority Date: 02/19/2008
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamashita, Hiroki, Fukuda, Koji
• Granted Patent: US 8,149,973 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value.

Claims

1. A clock recovery circuit for generating a recovery clock from an input data signal, comprising:

a first circuit that detects a phase difference between the input data signal and the recovery clock and outputs the phase difference;

a second circuit that averages the output of the first circuit and outputs the average;

a third circuit that samples and holds the output of the first circuit and outputs the held value; and

a fourth circuit that generates a clock having a phase corresponding to the sum of the integral value of the output of the second circuit and the output of the third circuit and outputs the clock as the recovery clock,

wherein the third circuit receives a burst transmission start signal, samples and holds the output of the first circuit, and outputs the held value, and

wherein the third circuit receives a burst transmission end signal, and resets the held value to an initial value.

5. The clock recovery circuit according to claim 1,

wherein the fourth circuit includes:

a sixth circuit that generates a clock having a phase corresponding to the integral value of the second circuit; and

a seventh circuit that changes the phase of an input clock by a value corresponding to the output of the third circuit or the fifth circuit, and

wherein the sixth circuit and the seventh circuit are connected to each other in a cascade manner.

6. The clock recovery circuit according to claim 5,

wherein the sixth circuit generates a clock having a frequency corresponding to the output of the second circuit.

7. The clock recovery circuit according to claim 5,

wherein the sixth circuit changes the phase of a clock supplied from the outside by a value corresponding to the integral value of the second circuit and outputs the changed clock.

8. The clock recovery circuit according to claim 5,

wherein the seventh circuit is a variable delay circuit that delays the phase of an input clock by a value corresponding to the output of the third circuit or the fifth circuit.

2. A clock recovery circuit for generating a recovery clock from an input data signal, comprising:

a first circuit that detects a phase difference between the input data signal and the recovery clock and outputs the phase difference;

a second circuit that averages the output of the first circuit and outputs the average;

a fifth circuit that samples and holds the output of the first circuit and outputs the held value; and

a fourth circuit that generates a clock having a phase corresponding to the sum of the integral value of the output of the second circuit and the output of the fifth circuit and outputs the clock as the recovery clock,

wherein the fifth circuit receives a burst transmission start signal, samples and holds the output of the first circuit, and outputs the held value, and

wherein the held value is changed to an initial value.

3. The clock recovery circuit according to claim 2,

wherein the fifth circuit includes:

a switch that performs switching between the output of the first circuit and the output of the fifth circuit; and

a capacitor and a resistor that are connected in parallel between the output of the fifth circuit and the ground, and

wherein the switch is turned on in response to the burst transmission start signal.

4. The clock recovery circuit according to claim 2,

wherein the change speed of the held value to the initial value by the fifth circuit is lower than the operation speed of the second circuit, and is shorter than each burst time width of the input data signal.