DIGITAL AUTOMATIC GAIN CONTROL

• US 20090208033A1
• Filed: 01/20/2009
• Published: 08/20/2009
• Est. Priority Date: 12/05/2000
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: ON Semiconductor Corporation
• Inventors: Sorensen, Bryant, Wahl, Jerry, Kindred, Jon Schmidt
• Application Number:
  US12/356,256
• Publication Number:
  US 20090208033A1
• Time in Patent Office: Days
• US Class Current: 381/104
• CPC Class Codes: H03G 1/04 Modifications of control circuit to reduce distortion caused by control modifications to reduce influence of variations of internal impedance of amplifying elements caused by control H03F1/08
• CPC Class Codes: H03G 3/3005 in amplifiers suitable for low-frequencies, e.g. audio amplifiers H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/301 the gain being continuously variable
• CPC Class Codes: H03G 7/08 incorporating negative feedback
• CPC Class Codes: H04R 25/356 Amplitude, e.g. amplitude shift or compression
• CPC Class Codes: H04R 25/505 using digital signal processing

Abstract

Systems, devices, and methods are provided to inhibit apparent amplitude modulation in non-linear processing that causes distortion in a processed signal. One aspect of the invention includes a hearing aid. The hearing aid includes a microphone to receive an input signal, a speaker to reproduce the input signal, and a processor. The processor processes the input signal using a gain. The processor includes an inhibitor, which inhibits distortions, and an adjuster, which adjusts the gain. The inhibitor acts to smooth an envelope of the input signal to inhibit undesired modulation. The adjuster adjusts the gain if the envelope is either above or below a threshold.

Claims

1. A digital analog gain control, comprising:

a detector to detect an envelope of an input signal using Hilbert filters;

an adder to provide a difference between the envelope and a threshold; and

an adjuster that adjust a gain if the difference is one of two conditions, wherein the two conditions includes being greater than zero and being less than zero.

2. The digital analog gain control of claim 1, further comprising a filter that removes low frequencies, wherein the filter receives the input signal, removes frequencies less than about 100 Hertz from the input signal, and presents the input signal to the detector.

3. The digital analog gain control of claim 2, further comprising a digital delay element that receives the input signal and presents a delayed input signal.

4. The digital analog gain control of claim 3, further comprising a first Hilbert filter and a second Hilbert filter, wherein the first Hilbert filter receives the delayed input signal and filters the delayed input signal to form the first filtered input signal, and wherein the second Hilbert filter receives the input signal and filters the input signal to form the second filtered input signal.

5. The digital analog gain control of claim 4, further comprising:

a first multiplier and a second multiplier, wherein the first multiplier receives the first filtered input signal and squares the first filtered input signal to form a first squared signal, and wherein the second multiplier receives the second filtered input signal and squares the second filtered input signal to form a second squared signal;

another adder to add the first squared signal and the second squared signal to form a sum-of-square signal; and

a limiter that receives the sum-of-square signal, limits the sum-of-square signal to a desired range, and presents a limited signal to the adder that provides the difference between the envelope and the threshold.

8. The digital analog gain control of claim 1, wherein:

the adjuster receives the difference, a release time constant, and an attack time constant, wherein the adjuster adjust a gain if the difference is one of two conditions, and wherein the adjuster decreases the gain if the difference is positive.

9. The digital analog gain control of claim 8, wherein:

the adjuster receives a previous gain,

wherein if the difference is negative, the adjuster increases the gain by shifting the bits of the previous gain to the right by the release time constant to form a new gain and taking the negative of the new gain, and

wherein if the difference is positive, the adjuster decreases the gain by shifting the bits of the difference to the right by the attack time constant to form the new gain.

11. The digital analog gain control of claim 9, further comprising:

a width adjuster that adjusts the word with of the previous gain and presents an adjusted previous gain;

another adder that adds the new gain and the adjusted previous gain to form the gain;

a limiter to the limit the range of the gain so that the gain is positive;

a buffer that stores the gain and presents the stored gain, wherein the stored gain is defined as the previous gain, which is presented to the adjuster and the width adjuster; and

a rounding circuit that rounds the stored gain to a smaller precision value so as to be compatible with the input width of subsequent circuitry that includes a digital-to-analog converter.

16. The digital analog gain control of claim 1, further comprising:

a filter to block low frequencies from the input signal;

and

wherein the adjuster receives the difference, a release time constant, and an attack time constant, wherein the adjuster increases the gain if the difference is negative, and wherein the adjuster decreases the gain if the difference is positive.

17. The digital analog gain control of claim 16, wherein:

the filter includes a first digital delay that receives the input signal and presents a delayed input signal;

the filter includes a first adder that determines a difference between the input signal and the delayed input signal;

the filter includes a first multiplier that multiplies the difference and a scale to form a scaled signal, wherein the scaled signal inhibits the filter from overflow.

20. The digital analog gain control of claim 17, wherein:

the filter includes a second adder that adds the scaled signal and a blocked signal to form a filtered signal;

the filter includes a second digital delay that receives the filtered signal and presents a filtered signal that is delayed; and

the filter includes a second multiplier that multiplies the filtered signal that is delayed and an alpha signal to form a blocked signal, wherein the alpha signal determines a range of frequencies that will be blocked by the filter.

6-7. -7. (canceled)

10. (canceled)

12-15. -15. (canceled)

18-19. -19. (canceled)

21-22. -22. (canceled)

23. A digital analog gain control, comprising:

a detector to detect an envelope of the input signal using infinite-impulse-response (IIR) filters;

an adder to provide a difference between the envelope and a threshold; and

an adjuster that receives the difference, a release time constant, and an attack time constant, wherein the adjuster adjust a gain if the difference is one of two conditions, wherein the two conditions includes being a negative number and being a positive number, wherein the adjuster increases the gain if the difference is negative, and wherein the adjuster decreases the gain if the difference is positive.

25. The digital analog gain control of claim 23, wherein each infinite-impulse-response filter includes a first delay, a second delay, and a scale element, wherein the input signal is delayed by the first delay, delayed by the second delay, and scaled by the scale element to form a scaled signal.

26. The digital analog gain control of claim 25, wherein:

each infinite-impulse response filter includes a first adder that determines a difference between the input signal and a feedback signal;

each infinite-impulse-response filter includes a multiplier that multiplies the difference and a beta signal to form a modified signal, wherein the beta signal modifies the phase of the difference;

each infinite-impulse-response filter includes a third delay that delays the modified signal to form a filtered signal; and

each infinite-impulse-response filter includes a fourth delay that delays the filtered signal to form the feedback signal.

24. (canceled)

27-29. -29. (canceled)

30. A method for controlling a gain of an amplifier, comprising:

forming an envelope of an input signal that lacks modulation using Hilbert filters; and

subtracting the envelope from a threshold to form a difference, wherein the difference is used to control the gain.

31. The method of claim 40, wherein blocking includes blocking low frequencies that are less than about 100 Hertz.

32. The method of claim 30, further comprising:

determining if the difference is greater than zero;

shifting the bits of the difference to the right by an attack constant to form a decreased gain; and

shifting the bits of a negated signal to the right by a release constant to form an increased gain.

35. The method of claim 32, further comprising switching for presenting the decreased gain as the gain if the difference is greater than zero, or else the act of switching presents the increased gain as the gain if the difference is less than zero.

36. The method of claim 35, further comprising:

summing the gain and the feedback signal that is delayed to form a modified gain signal;

presenting a final gain to an analog-to-digital converter, wherein the final gain is zero if the modified gain signal is less than or equal to zero, and wherein the final gain is one if the modified gain signal is greater than one;

delaying the final rain to produce the feedback signal that is delayed; and

negating the feedback signal that is delayed to form the negated signal.

40. The method of claim 30, further comprising blocking low frequencies from the input signal.

33-34. -34. (canceled)

37-39. -39. (canceled)