Code division multiplex signal receiving apparatus and code division multiplex transmitting and receiving system

• US 20090208213A1
• Filed: 01/27/2009
• Published: 08/20/2009
• Est. Priority Date: 02/20/2008
• Status: Active Grant

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Sarashina, Masahiro
• Granted Patent: US 8,073,000 B2
• Time in Patent Office: Days
• US Class Current: 398/77
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2201/70715 with application-specific features
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713

Abstract

In a code division multiplex transmitting and receiving system, the transmitting apparatus inserts a clock signal in the code division multiplex signal. The clock signal has a frequency equal to a null frequency in the frequency spectrum of the code division multiplex signal. The receiving apparatus extracts this frequency component from the received signal and recovers the clock signal, using an ordinary clock recovery device of the type designed to recover a clock signal from a bi-level signal. The recovered clock signal is used as a synchronizing signal in the processing of the received signal.

Claims

1. A code division multiplex signal receiving apparatus for use in a code division multiplex transmitting and receiving system, wherein the code division multiplex signal receiving apparatus:

receives a clocked code division multiplex signal generated by combining a code division multiplex signal with a clock signal having a frequency equal to a null frequency disposed in a void in a frequency spectrum of the code division multiplex signal;

extracts a first frequency component of the clocked code division multiplex signal, the first frequency component including the frequency of the clock signal; and

recovers the clock signal from the first frequency component.

2. The code division multiplex signal receiving apparatus of claim 1, wherein said null frequency is a chip-rate frequency of the code division multiplex signal.

3. The code division multiplex signal receiving apparatus of claim 1, wherein the code division multiplex signal receiving apparatus comprises:

a bandpass filter for extracting the first frequency component; and

a clock recovery device for recovering the clock signal from the first frequency component.

4. The code division multiplex signal receiving apparatus of claim 3, further comprising:

a band elimination filter for eliminating a second frequency component including the frequency of the clock signal from the clocked code division multiplex signal to obtain a received code division multiplex signal; and

a received signal processor for processing the received code division multiplex signal in synchronization with the clock signal recovered by the clock recovery device.

5. The code division multiplex signal receiving apparatus of claim 4, wherein the code division multiplex signal is organized into frames having a first length, and the received signal processor includes a gating unit operable in synchronization with the recovered clock signal to open and close a window having a second length greater than the first length and pass the received code division multiplex signal only while the window is open.

6. The code division multiplex signal receiving apparatus of claim 5, wherein the bandpass filter has a passband width substantially equal to a reciprocal of a difference between the first length and the second length.

7. A code division multiplex transmitting and receiving system, comprising a code division multiplex signal transmitting apparatus and at least one code division multiplex signal receiving apparatus, wherein:

the code division multiplexed transmitting apparatus comprises

a code division multiplex signal transmitting section for encoding transmit signals on a plurality of channels to generate respective coded transmit signals, and multiplexing the coded transmit signals to generate a code division multiplex signal,

a clock signal generator for generating and outputting a clock signal having a frequency equal to a null frequency disposed in a void in a frequency spectrum of the code division multiplex signal, and

a clock signal combiner for combining the code division multiplex signal and the clock signal to generate a clocked code division multiplex signal and transmitting the clocked code division multiplex signal to the code division multiplex signal receiving apparatus; and

the code division multiplex signal receiving apparatus comprises

a code division multiplex signal splitter for receiving the clocked code division multiplex signal and splitting the clocked code division multiplex signal into a first clocked code division multiplex signal and a second clocked code division multiplex signal,

a band elimination filter for receiving the first clocked code division multiplex signal and eliminating a first frequency component including the frequency of the clock signal to obtain a coded received signal,

a received signal processor for receiving the coded received signal, decoding the coded received signal, recovering the received signal, and outputting the received signal;

a bandpass filter for receiving the second clocked code division multiplex signal, extracting a second frequency component including the frequency of the clock signal from the second clocked code division multiplex signal, and outputting the second frequency component; and

a clock recovery device for recovering the clock signal from the second frequency component.

8. The code division multiplex transmitting and receiving system of claim 7, wherein said null frequency is a chip-rate frequency of the code division multiplex signal.

9. The code division multiplex transmitting and receiving system of claim 7, wherein the code division multiplex signal transmitting section comprises:

first to N-th transmit signal processing units for generating and outputting coded transmit signals for first to N-th channels, where N is an integer greater than one; and

a coded signal combiner for combining the coded transmit signals output from the first to the N-th transmit signal processing units.

10. The code division multiplex transmitting and receiving system of claim 9, wherein each of the first to the N-th transmit signal processing units comprises:

a header attachment unit for generating a transmit signal by adding a header to a bi-level digital transmit signal and outputting the bi-level digital transmit signal with the header;

a coding unit for receiving and encoding the bi-level digital transmit signal with the header and outputting a resulting coded transmit signal; and

a transmit timing adjustment unit for receiving the coded transmit signal and adjusting a transmitting timing thereof.

11. The code division multiplex transmitting and receiving system of claim 7, wherein the received signal processor comprises:

a decoding unit for decoding the coded received signal and outputting the decoded received signal;

a gating processor for gating the decoded received signal; and

a header remover for eliminating a header of the decoded received signal output from the gating processor and outputting the received signal.

12. The code division multiplex transmitting and receiving system of claim 7, wherein the code division multiplex signal is organized into frames having a first length, and the gating unit operates in synchronization with the recovered clock signal to open and close a window having a second length greater than the first length and pass the received code division multiplex signal only while the window is open.

13. The code division multiplex transmitting and receiving system of claim 12, wherein the bandpass filter has a passband width substantially equal to a reciprocal of a difference between the first length and the second length.

14. The code division multiplex transmitting and receiving system of claim 7, further comprising a passive optical network through which the code division multiplex signal transmitting apparatus and code division multiplex signal receiving apparatus are interconnected.