SYSTEM AND METHOD TO PREDICT CHIP IDDQ AND CONTROL LEAKAGE COMPONENTS

• US 20090210201A1
• Filed: 02/14/2008
• Published: 08/20/2009
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bickford, Jeanne P. Spence, McMahon, Robert, Habib, Nazmul
• Granted Patent: US 9,117,045 B2
• Time in Patent Office: Days
• US Class Current: 703/2
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.

Claims

1. A method for creating a leakage model, comprising:

placing an integrated circuit quiescent current (IDDQ) prediction macro in a plurality of design topographies;

collecting data using the IDDQ prediction macro;

measuring subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines;

establishing a leakage model;

correlating the semiconductor test site measurements to the scribe line measurements to establish scribe line control limits;

predicting product leakage; and

setting subthreshold leakage limits and gate leakage limits for each product using the leakage model.

2. The method of claim 1, wherein the IDDQ prediction macro is a scalable parametric measurement macro configured to measure the subthreshold leakage and the gate leakage in the semiconductor test site and in the scribe lines.

3. The method of claim 1, wherein the establishing a leakage model is performed using product to hardware information from the semiconductor test site and the scribe lines.

4. The method of claim 1, wherein the plurality of design topographies include at least one of different densities and shapes.

5. The method of claim 1, wherein the collecting data is performed using a plurality of IDDQ prediction macros.

6. The method of claim 1, wherein the measuring the subthreshold leakage and the gate leakage for the at least one device type occurs at one or more of the semiconductor test site and the scribe line.

7. The method of claim 1, wherein the scribe line control limits are configured to be used during semiconductor fabrication.

8. The method of claim 1, wherein the leakage model is established using product to hardware information from the semiconductor test site.

9. A method for analyzing product yields, comprising:

providing a computer infrastructure operable to;

set subthreshold leakage limits and gate leakage limits for a product using a leakage model;

screen the product to obtain subthreshold leakage and gate leakage yield losses;

determine whether one or more of the subthreshold leakage and the gate leakage exceed the subthreshold leakage limits and gate leakage limits; and

provide feedback if one or more of the subthreshold leakage limits and the gate leakage limits are exceeded.

10. The method of claim 9, wherein the providing feedback includes one or more of identifying the location of the leakage and what type of leakage occurred.

11. The method of claim 9, further comprising scraping the product if one or more of the subthreshold leakage limits and the gate leakage limits are exceeded.

12. The method of claim 9, further comprising tracking the subthreshold leakage and gate leakage yield losses and adjusting the leakage model based on the subthreshold leakage and gate leakage yield losses.

13. The method of claim 9, further comprising providing feedback if an overall leakage limit is exceeded.

14. The method of claim 13, wherein the overall leakage is the sum of the subthreshold leakage and the gate leakage.

15. A computer program product comprising a computer usable medium having readable program code embodied in the medium, the computer program product includes at least one component to:

measure subthreshold leakage and gate leakage using an IDDQ prediction macro;

create a leakage model using the measurements collected from the IDDQ prediction macro;

correlate a product'"'"'s scribe line measurements to the measurements collected from the IDDQ prediction macro;

track yield losses for the subthreshold leakage and the gate leakage of the product; and

determine whether the subthreshold leakage and/or the gate leakage of the product has been exceeded based on the model.

16. The computer program product of claim 15, further comprising a component to provide feedback if the subthreshold leakage and/or the gate leakage exceeds an expected leakage, which is determined at least in part from the measurements collected from the IDDQ prediction macro.

17. The computer program product of claim 16, wherein the feedback includes one or more of identifying the location of the leakage and what type of leakage occurred.

18. The computer program product of claim 15, further comprising a component to adjust the leakage model based on the yield losses.

19. The computer program product of claim 15, wherein the subthreshold leakage and gate leakage are measured at a semiconductor test site and in scribe lines using the IDDQ prediction macro.

20. The computer program product of claim 15, wherein the subthreshold leakage and the gate leakage are measured using a plurality of IDDQ prediction macros.