BUS INTERCONNECT DEVICE AND A DATA PROCESSING APPARATUS INCLUDING SUCH A BUS INTERCONNECT DEVICE

• US 20090210594A1
• Filed: 08/04/2006
• Published: 08/20/2009
• Est. Priority Date: 08/04/2006
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Tune, Andrew David, Bruce, Alistair Crone
• Granted Patent: US 8,171,191 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: H01P 3/02 with two longitudinal conductors

Abstract

A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.

Claims

1. A parallel plate waveguide interconnect for coupling together a plurality of devices.

2. A bus interconnect device comprising a parallel plate waveguide for coupling together a plurality of devices.

3. A bus interconnect device as claimed in claim 2 further comprising at least one via for coupling a device in to the parallel plate waveguide.

4. A bus interconnect device as claimed in claim 2 or claim 3, wherein said plurality of devices are arranged to communicate via signals propagated through the parallel plate waveguide using an ultra wideband communication protocol.

5. A bus interconnect device as claimed in any of claims 2 to 4, wherein said plurality of devices are arranged to communicate via RF signals propagated through the parallel plate waveguide.

6. A bus interconnect device as claimed in any of claims 2 to 4, wherein said plurality of devices are arranged to communicate via optical signals propagated through the parallel plate waveguide.

7. A chip comprising a plurality of functional blocks coupled together by a bus interconnect device as claimed in any of claims 2 to 6.

8. A chip as claimed in claim 7 wherein the functional blocks are connected to the interconnect by a transmitter or a receiver coupled to an antenna disposed within the parallel plate waveguide.

9. A chip as claimed in claim 7 or claim 8, wherein existing infrastructure of the chip is used to form the parallel plate waveguide.

10. A chip as claimed in claim 9, wherein the existing infrastructure is an existing power distribution infrastructure.

11. A chip as claimed in claim 7 or claim 8, wherein a power distribution infrastructure of the chip is replicated to form the parallel plate waveguide.

12. A chip as claimed in any of claims 7 to 11, where the plurality of functional blocks comprise an array of processing elements.

13. A chip as claimed in claim 12, wherein the plurality of functional blocks are further coupled via a wired bus network, the parallel plate waveguide being used for global communication amongst the array of processing elements.

14. A multi-chip module comprising a plurality of chips mounted on a substrate, the substrate including a bus interconnect device as claimed in any of claims 2 to 6.

15. A multi-chip module as claimed in claim 14 wherein the parallel plate waveguide is constructed using existing power planes of the multi-chip module substrate.

16. A multi-chip module as claimed in claim 14 wherein power planes of the multi-chip module substrate are replicated to form the parallel plate waveguide.

17. A printed circuit board (PCB) for receiving at least one chip, the PCB comprising a bus interconnect device as claimed in any of claims 2 to 6.

18. A PCB as claimed in claim 17 wherein the parallel plate waveguide is constructed using existing power planes of the PCB.

19. A PCB as claimed in claim 17 wherein power planes of the PCB are replicated to form the parallel plate waveguide.

20. A microprocessor or microprocessor peripheral device including a bus interconnect device as claimed in any of claims 2 to 6.