POWER SEMICONDUCTOR DEVICE INCLUDING A DOUBLE METAL CONTACT

• US 20090212435A1
• Filed: 02/25/2008
• Published: 08/27/2009
• Est. Priority Date: 02/25/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Jones, David Paul, Burke, Hugo, Parsonage, Philip, Johns, Susan, Montgomery, Robert
• Granted Patent: US 8,791,525 B2
• Time in Patent Office: Days
• US Class Current: 257/759
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11019 for protecting parts during the process
• CPC Class Codes: H01L 2224/11466 Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/05494 : having an amorphous microstructure, i.e. glass
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Claims

1. A power semiconductor device comprising:

a semiconductor body including an active region on one surface thereof, said active region including source regions and gate electrodes;

a first metal layer disposed on said one surface and coupled to said source regions;

a metallic gate bus disposed on said one surface lateral to and spaced from said first metal layer;

a buffer body disposed over said gate bus and in a space between said gate bus and said first metal layer; and

a second metal layer disposed over said first metal layer and extending over said buffer body.

2. The power semiconductor device of claim 1, wherein said first metal layer and said gate bus are less than 2 microns thick.

3. The power semiconductor device of claim 1, wherein said second metal layer is more then 4 microns thick.

4. The power semiconductor device of claim 1, wherein said second metal layer is more then 4-20 microns thick.

5. The power semiconductor device of claim 1, wherein said buffer body is comprised of polyimide.

6. The power semiconductor device of claim 1, further comprising a hermetic sealant body disposed between said gate bus and said buffer body.

7. The power semiconductor device of claim 6, wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.

8. A method of fabricating a power semiconductor device, comprising:

depositing a first metal layer over an active region formed in a semiconductor body, said active region including source regions and gate electrodes;

dry etching said first metal layer to obtain a first source metal layer and a metallic gate bus that is laterally spaced from said first source metal layer;

forming a buffer body over said gate bus; and

depositing a second metal layer over said first metal layer and over said buffer body.

9. The power semiconductor device of claim 8, wherein said first metal layer and said gate bus are less than 2 microns thick.

10. The power semiconductor device of claim 8, wherein said second metal layer is more than 4 microns thick.

11. The power semiconductor device of claim 8, wherein said second metal layer is more than 4-20 microns thick.

12. The power semiconductor device of claim 8, wherein said buffer body is comprised of polyimide.

13. The power semiconductor device of claim 8, further comprising a hermetic sealant body disposed between said gate bus and said buffer body.

14. The power semiconductor device of claim 13, wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.