Semiconductor device

• US 20090212440A1
• Filed: 02/05/2009
• Published: 08/27/2009
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kanamori, Kohji
• Granted Patent: US 8,716,866 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

An object of the present invention is to solve the problem that the number of pads increases due to high packaging density and the size of semiconductor devices increases due to increase of the pad density. A semiconductor device according to the present invention uses a conductor trace on an interconnection substrate to interconnect two nonadjacent pads.

Claims

1. A semiconductor device comprising:

a semiconductor chip including a plurality of pads and a plurality of external connection terminals; and

an interconnection substrate including an interconnection pattern connecting the plurality of pads to said external connection terminals;

wherein a first pad among the plurality of pads and a second pad that is not adjacent to the first pad are interconnected by the interconnection pattern.

2. The semiconductor device according to claim 1, wherein the plurality of pads are arranged in line in the center of the semiconductor chip in a first direction.

3. The semiconductor device according to claim 2, wherein a main line of the interconnection pattern extends in parallel to the first direction.

4. The semiconductor device according to claim 3, wherein the interconnection pattern includes a branch line connecting the first pad to the main line.

5. The semiconductor device according to claim 4, wherein the branch line runs from the main line and passes over one of the plurality of pads other than the first pad to connect to the first pad.

6. The semiconductor device according to claim 1, wherein the number of the plurality of pads is greater than the number of the external connection terminals.

7. The semiconductor device according to claim 1, wherein the first and second pads are of the same electric potential or signal.

9. The semiconductor device according to claim 2, wherein the plurality of pads are arranged in two lines with the main line between the two lines of the pads.

10. The semiconductor device according to claim 9, wherein the first pad is in one of the two lines along the main line and the second pad is in the other of the two lines along the main line.

8. A semiconductor device comprising:

a semiconductor chip including a plurality of pads; and

an interconnection substrate including an interconnection pattern connecting the semiconductor chip to an external connection terminal;

wherein first pad of said pads, first branch of the interconnection pattern, the external connection terminal, second branch of the interconnection pattern, and second pad of said pads are disposed in this order between said first and said second pads.