ISOLATION CIRCUIT

• US 20090212810A1
• Filed: 05/07/2009
• Published: 08/27/2009
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cram, Daniel P., Attalla, Hani S.
• Granted Patent: US 8,004,297 B2
• Time in Patent Office: Days
• US Class Current: 324/762.50
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.

Claims

1. An isolation circuit, comprising:

a first transistor configured for connection to a supply voltage via a first terminal;

a register connected to the first transistor;

a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and

wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.

2. The isolation circuit of claim 1, wherein the first terminal is connected to a source of the first transistor

3. The isolation circuit of claim 1, wherein the register is connected to a drain of the first transistor.

4. The isolation circuit of claim 1, wherein the first terminal is connected to a source of the second transistor.

5. The isolation circuit of claim 1, wherein the first terminal is connected to a source of the first transistor and to a source of the second transistor.

6. The isolation circuit of claim 1, wherein the first terminal is a supply voltage pad of a semiconductor die.

7. The isolation circuit of claim 1, wherein a short at the first terminal prevents the register from being loaded such that the state of the second transistor is an off state.

8. The isolation circuit of claim 1, wherein the register is loaded when the first terminal is unshorted such that the state of the second transistor is an on state.

9. The isolation circuit of claim 1, wherein the isolation circuit is located on an unsingulated semiconductor die.

10. The isolation circuit of claim 1, wherein the second terminal is connected to testing circuitry.

11. The isolation circuit of claim 10, wherein the testing circuitry includes at least one of:

built in self stress (BISS) circuitry; and

built in self test (BIST) circuitry.

12. The isolation circuit of claim 1, wherein the gate of the second transistor is connected to an output of an inverter, the input of the inverter being connected to the output of the register.

13. The isolation circuit of claim 1, including a pull down transistor connected to the output of the register.

14. The isolation circuit of claim 1, wherein the first terminal is a first Vcc input terminal of an unsingulated semiconductor die and the second terminal is a second Vcc input terminal of the unsingulated semiconductor die.

15. The isolation circuit of claim 1, wherein the first transistor is a p-channel transistor.

16. An isolation circuit, comprising:

a resistor connected in parallel with a first transistor to a first supply voltage input terminal;

a register having an output connected to a gate of the first transistor, the register connected to the first supply voltage input terminal; and

wherein the register is operable to control a state of the first transistor.

17. The isolation circuit of claim 16, wherein the register is operable to:

turn the first transistor off when the first supply voltage input terminal is shorted; and

turn the first transistor on when the first supply voltage input terminal is unshorted.

18. The isolation circuit of claim 16, wherein the output of the register is connected to the gate of the first transistor via an inverter.

19. The isolation circuit of claim 16, wherein a first side of the resistor is connected to the first supply voltage terminal and a second side of the resistor is connected to a second supply voltage input terminal.

20. The isolation circuit of claim 19, wherein the second supply voltage terminal is connected to on-die testing circuitry.

21. An isolation circuit, comprising:

a resistor connected in parallel with a first transistor to a first supply voltage input terminal;

a register having an output connected to a gate of the first transistor, the register connected to the first supply voltage input terminal;

a second transistor connected between the first supply voltage input terminal and the register; and

wherein the register is operable to control a state of the first transistor.

22. The isolation circuit of claim 21, wherein a gate of the second transistor is connected to an enable input.

23. The isolation circuit of claim 21, including a pull down transistor connected to the output of the register.

24. The isolation circuit of claim 21, wherein the resistor is connected to a second supply voltage terminal, the second supply voltage terminal coupled to testing circuitry;

and wherein a status of the register controls the state of the first transistor such that;

a first amount of current is drawn, in response to a particular potential applied to the first supply voltage terminal, when a die to which the isolation circuit is connected is a functional die; and

a different amount of current is drawn, in response to the particular potential applied to the first supply voltage terminal, when the die to which the isolation circuit is connected is a nonfunctional die.

25. The isolation circuit of claim 24, wherein the different amount of current is less than the first amount of current.