RESISTANCE CHANGE MEMORY DEVICE

• US 20090213639A1
• Filed: 02/20/2009
• Published: 08/27/2009
• Est. Priority Date: 02/25/2008
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TODA, Haruki
• Granted Patent: US 8,004,873 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.

Claims

1. A resistance change memory device comprising:

a memory cell array, which includes a plurality of first wirings, a plurality of second wirings so disposed as to cross the first wirings, and memory cells disposed at the cross points of the first and second wirings, the memory cell including a diode and a variable resistance element connected in series, the diode being disposed with such a polarity that anode thereof is located on the first wiring side, wherein

the memory cell array is sequentially set in the following three states after power-on;

a waiting state defined by that both the first and second wirings are set at a first voltage;

a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and

an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively, a selected memory cell being read or written in the access state.

2. The resistance change memory device according to claim 1, wherein

a defect detection operation is performed in the standby state of the memory cell array in such a way as to detect a defective wiring based on cell current of a defective cell with a degraded diode coupled to the defective wiring, and set the defective wiring in a floating and unused state.

3. The resistance change memory device according to claim 1, further comprising:

a defect detection circuit configured to detect a defective second wiring in the memory cell array in the standby state based on cell current of a defective cell with a degraded diode coupled to the defective second wiring, and set the defective second wiring in a floating and unused state.

4. The resistance change memory device according to claim 1, wherein

the memory cell array is divided into a plurality of units each defined as a range including a plurality of the wirings, and further comprising:

defect detection circuits prepared for the respective units so as to detect a defective wiring, to which a defective cell with a degraded diode is coupled, and set the defective wiring in a floating and unused state.

5. The resistance change memory device according to claim 4, further comprising:

power supply circuits prepared for the respective units for setting the second wirings at the second voltage in the standby state; and

switch circuits prepared for the respective units for coupling selected ones in the second wirings to the corresponding sense amplifiers.

6. The resistance change memory device according to claim 5, wherein

the defect detection circuit includes a latch circuit, which is reset in the waiting state and detects the voltage drop of the second wiring so as to generate and latch an error flag, and wherein

the corresponding ones are off-driven by the error flag.

7. The resistance change memory device according to claim 4, wherein

the memory cell array includes a spare unit to be accessed in place of defective one in the units in accordance with the defect detection circuit.

8. The resistance change memory device according to claim 1, wherein

the memory cell array is formed of multiple layers stacked.

9. The resistance change memory device according to claim 1, further comprising:

a current cutter circuit configured to be coupled to selected one of the second wirings in the memory cell array in a program mode, and monitor cell current to detect program completion, thereby cutting the cell current.

10. A resistance change memory device comprising:

a memory cell array, which includes a plurality of first wirings, a plurality of second wirings so disposed as to cross the first wirings, and memory cells disposed at the cross points of the first and second wirings, the memory cell including a diode and a variable resistance element connected in series, the diode being disposed with such a polarity that anode thereof is located on the first wiring side; and

a defect detection circuit configured to detect a defective second wiring, to which a defective cell with a degraded diode is coupled, in such a standby state of the memory cell array that the diodes of the memory cells are reverse-biased, and set the defective second wiring in a floating and unused state.

11. The resistance change memory device according to claim 10, wherein

the memory cell array is sequentially set in the following three states after power-on:

a waiting state defined by that both the first and second wirings are set at a first voltage;

the standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and

an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively, a selected memory cell being read or written in the access state.

12. The resistance change memory device according to claim 10, wherein

the memory cell array is divided into a plurality of units each defined as a range including a plurality of the second wirings, and wherein

a plurality of the defect detection circuits are prepared for the respective units.

13. The resistance change memory device according to claim 12, further comprising:

power supply circuits prepared for the respective units for setting the second wirings at the second voltage in the standby state; and

switch circuits prepared for the respective units for coupling selected ones in the second wirings to the corresponding sense amplifiers.

14. The resistance change memory device according to claim 12, wherein

the defect detection circuit includes a latch circuit, which is reset in the waiting state and detects the voltage drop of the second wiring so as to generate and latch an error flag, and wherein

the corresponding ones in the power supply circuits and the switch circuits are off-driven by the error flag.

15. The resistance change memory device according to claim 12, wherein

the memory cell array includes a spare unit to be accessed in place of defective one of the units in accordance with the defect detection circuit.

16. The resistance change memory device according to claim 10, wherein

the memory cell array is formed of multiple layers stacked.

17. The resistance change memory device according to claim 10 further comprising:

a current cutter circuit configured to be coupled to selected one of the second wirings in the memory cell array in a program mode, and monitor cell current to detect program completion, thereby cutting the cell current.