Balanced Bufferless Switch

• US 20090214208A1
• Filed: 04/21/2009
• Published: 08/27/2009
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Rockstar Consortium US LP (Rockstar Consortium Inc.)
• Inventors: Beshai, Maged E.
• Granted Patent: US 8,139,570 B2
• Time in Patent Office: Days
• US Class Current: 398/52
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 2011/0024 using space switching
• CPC Class Codes: H04Q 2011/0033 using time division switching
• CPC Class Codes: H04Q 2011/0052 Interconnection of switches

Abstract

A high capacity distributed switching system comprises electronic edge nodes connected to a balanced bufferless switch which may be electronic or optical. The balanced bufferless switch comprises a balanced connector and a switch fabric. The balanced connector comprises an array of temporally cyclic rotator units having graduated rotation shifts and each having a prime number of output ports. The switch fabric may be a mesh interconnection of switch modules. Due to the use of the balanced connector, establishing a path through the switch fabric requires at most a second-order time-slot matching process for a high proportion of connection requests with a much reduced need for a third-order time-slot matching process required in a conventional mesh structure.

Claims

1. A balanced connector comprising:

a plurality of input ports; and

a plurality of output ports, said output ports divided into a number of output groups each output group including at least two output ports;

said balanced connector operable to change the connectivity of said input ports to said output ports during successive time intervals in a time frame having a predefined number of time intervals so that;

during any two successive time intervals, each input port connects to output ports in different output groups;

during said time frame each input port connects to an output port in each output group; and

during said time frame, any combination of two input ports connects only once to output ports of the same output group.