TELEMETRY DOUBLE BUFFERING AND OVERSAMPLING FOR AN IMPLANTABLE MEDICAL DEVICE

• US 20090216297A1
• Filed: 12/01/2008
• Published: 08/27/2009
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Harris, Thomas J., Balczewski, Ron A.
• Granted Patent: US 8,406,891 B2
• Time in Patent Office: Days
• US Class Current: 607/60
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: A61N 1/37254 Pacemaker or defibrillator security, e.g. to prevent or inhibit programming alterations by hackers or unauthorised individuals
• CPC Class Codes: A61N 1/3727 characterised by the modulation technique
• CPC Class Codes: A61N 1/37276 characterised by means for reducing power consumption during telemetry
• CPC Class Codes: G08C 17/00 Arrangements for transmitting signals characterised by the use of a wireless electrical link

Abstract

This document discusses, among other things, a communication circuit for an IMD comprising a radio frequency (RF) modulator to modulate and demodulate IMD data signals, first and second serial buffer registers to store received demodulated data and to store transmit data for modulation and configured to operate according to a first clock signal, and a parallel buffer register to receive data in parallel from the first and second serial buffer registers and configured to operate according to a second clock signal that is slower than the first clock signal. The communication circuit also includes a telemetry control circuit configured to, when in the receive mode, alternate between serially receiving data into the first serial buffer register while the parallel buffer receives data from the second serial buffer register, and serially receiving data into the second serial buffer register while the parallel buffer receives data from the first serial buffer.

Claims

1. A communication circuit for an implantable medical device (IMD) comprising:

a radio frequency (RF) modulator configured to modulate an outgoing IMD data signal and to demodulate an incoming IMD data signal;

a first serial buffer register, communicatively coupled to the RF modulator, configured to store received demodulated data and to store transmit data for modulation, wherein the first serial buffer register operates according to a first clock signal;

a second serial buffer register, communicatively coupled to the RF modulator, configured to store received demodulated data and to store transmit data for modulation, wherein the second serial buffer register operates according to the first clock signal;

a parallel buffer register, communicatively coupled to the first and second serial buffer registers, configured to receive data in parallel from the first and second serial buffer registers, wherein the parallel buffer register operates according to a second clock signal that is slower than the first clock signal; and

a telemetry control circuit, communicatively coupled to the first serial buffer register, the second serial buffer register, and the parallel buffer, wherein the telemetry control circuit is configured to, when in the receive mode, alternate between serially receiving data into the first serial buffer register while the parallel buffer receives data from the second serial buffer register, and serially receiving data into the second serial buffer register while the parallel buffer receives data from the first serial buffer.

2. The communication circuit of claim 1, wherein the telemetry control circuit is configured to, when in the transmit mode, alternate between sending data to the RF modulator from the first serial buffer register while the second serial buffer register receives data from the parallel buffer register, and sending data to the RF modulator from the second serial buffer register while the first serial buffer register receives data from the parallel buffer register.

3. The communication circuit of claim 2, including byte level logic communicatively coupled to the parallel buffer register, wherein the byte level logic is configured to encode the data to be sent to the RF modulator, wherein the encoding limits the number of same-value bits in a bit string.

4. The communication circuit of claim 1, including a sampling circuit communicatively coupled to the RF modulator and the serial shift registers, wherein the sampling circuit is configured to:

obtain a specified number of sampled values of the data signal during a specified bit time; and

determine a bit value according to a majority rule applied to the specified number of sampled values.

5. The communication circuit of claim 1, wherein the telemetry control circuit is configured to activate at least a portion of the communication circuit when a boundary character is received into the serial register.

6. The communication circuit of claim 5, wherein the boundary character includes a comma character.

7. The communication circuit of claim 5, wherein the telemetry control circuit is configured to declare a communication message boundary when the boundary character is subsequently received into the serial register.

8. The communication circuit of claim 5, including an analog attenuator circuit communicatively coupled to the RF modulator circuit, and wherein the telemetry control circuit is configured to adjust a data signal amplitude while receiving at least a portion of the boundary character.

9. A method comprising:

demodulating a data signal incoming to an IMD;

serially storing demodulated data received in the data signal in a first serial buffer register;

transferring the received demodulated data to a parallel buffer register from the first serial buffer register, wherein the parallel buffer register operates according to a clock signal that is slower than a clock signal used to operate a serial buffer register;

switching the serial storing of demodulated data to a second serial buffer register during the transferring of the received demodulated data to the parallel buffer register; and

alternating the serial storing of the received data between the first and second serial buffer registers.

10. The method of claim 9, including:

transferring data from the parallel buffer register to the first serial buffer register;

serially sending data to a modulator from the first serial buffer register; and

alternating between transferring data from the parallel buffer register to the second serial buffer register during the serial sending of data by the first serial buffer register and transferring data from the parallel buffer register to the first serial buffer register during the sending of data by the second serial buffer register.

11. The method of claim 10, wherein serially sending data to a modulator includes encoding the data, wherein the encoding limits the number of same-value bits in a bit string message.

12. The method of claim 9, including:

sampling the received data signal a specified number of times during a specified bit time to obtain a specified number of samples of a bit value; and

determining the bit value according to a majority rule applied to the specified number of samples.

13. The method of claim 9, including activating circuits in the IMD when a boundary character is received into the first serial buffer register.

14. The method of claim 13, wherein activating circuits in the IMD includes activating the circuits when the boundary character includes a comma character.

15. The method of claim 13, including declaring a communication message boundary in the IMD when the boundary character is subsequently received into at least one of the first and second serial buffer registers.

16. The method of claim 15, including using at least a portion of the boundary character to adjust an attenuation threshold in a transceiver circuit of the IMD.

17. A system comprising an IMD and an external device to communicate with the IMD, wherein the IMD includes:

a radio frequency (RF) modulator configured to modulate an outgoing IMD data signal and to demodulate an incoming MD data signal;

a first serial buffer register, communicatively coupled to the RF modulator, configured to store received demodulated data and to store transmit data for modulation, wherein the first serial buffer register operates according to a first clock signal;

a second serial buffer register, communicatively coupled to the RF modulator, configured to store received demodulated data and to store transmit data for modulation, wherein the second serial buffer register operates according to the first clock signal;

a parallel buffer register, communicatively coupled to the first and second serial buffer registers, configured to receive data in parallel from the first and second serial buffer registers, wherein the parallel buffer register operates according to a second clock signal that is slower than the first clock signal; and

a telemetry control circuit, communicatively coupled to the first serial buffer register, the second serial buffer register, and the parallel buffer, wherein the telemetry control circuit is configured to, when in the receive mode, alternate between serially receiving data into the first serial buffer register while the parallel buffer receives data from the second serial buffer register, and serially receiving data into the second serial buffer register while the parallel buffer receives data from the first serial buffer.

18. The system of claim 17, wherein the telemetry control circuit is configured to, when in the transmit mode, alternate between sending data to the RF modulator from the first serial buffer register while the second serial buffer register receives data from the parallel buffer register, and sending data to the RF modulator from the second serial buffer register while the first serial buffer register receives data from the parallel buffer register.

19. The system of claim 17, wherein the external device is configured to serially send encoded data in a bit string to the IMD, wherein the encoding limits the number of same-value bits in the bit string.

20. The system of claim 19, wherein the external device is configured to serially send data encoded with 8 b/10 b encoding in the bit string to the IMD.