MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY

• US 20090216937A1
• Filed: 02/25/2009
• Published: 08/27/2009
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YASUFUKU, Kenta
• Granted Patent: US 8,151,036 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data.

Claims

1. A memory controller that controls access to a flash memory in which data is written in a page size unit according to data-write request information, wherein

the memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to the data-write request information does not match the page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data.

2. The memory controller according to claim 1, wherein the memory controller adds the dummy data to the write data of which a specific address is designated as a data transfer source in the instruction information to adjust the size of the write data to the page size unit.

3. The memory controller according to claim 1, wherein the memory controller adds the dummy data to the write data to which a specific flag is added in the instruction information to adjust the size of the write data to the page size unit.

4. The memory controller according to claim 1, wherein the flash memory is a NAND flash memory.

5. The memory controller according to claim 1, wherein the memory controller includes a direct memory access (DMA) controller that controls a DMA transfer to the flash memory, and

the DMA controller outputs write data of which the size does not match the page size unit of the flash memory, among the entire write data to be written into the flash memory by adjusting the size of the write data to the page size unit.

6. The memory controller according to claim 1, wherein the memory controller includes an error correction code (ECC) circuit that generates an ECC to be added to the write data to be written into the flash memory and uses the ECC added to the write data to perform an error detection correction of data read from the flash memory.

7. The memory controller according to claim 6, wherein the ECC circuit generates the ECC to be added to the write data and the dummy data that are to be written into the flash memory.

8. A memory system comprising:

the memory controller according to claim 1;

a flash memory configured to store therein data and that is accessed by the memory controller to read the data; and

a memory configured to store therein the instruction information.

9. The memory system according to claim 8, wherein the memory controller adds the dummy data to the write data of which a specific address is designated as a data transfer source in the instruction information to adjust the size of the write data to the page size unit.

10. The memory system according to claim 8, wherein the memory controller adds the dummy data to the write data to which a specific flag is added in the instruction information to adjust the size of the write data to the page size unit.

11. The memory system according to claim 8, wherein the flash memory is a NAND flash memory.

12. The memory system according to claim 8, wherein the memory controller includes a direct memory access (DMA) controller that controls a DMA transfer to the flash memory, and

the DMA controller outputs write data of which the size does not match the page size unit of the flash memory, among the entire write data to be written into the flash memory by adjusting the size of the write data to the page size unit.

13. The memory system according to claim 8, wherein the memory controller includes an error correction code (ECC) circuit that generates an ECC to be added to the write data to be written into the flash memory and uses the ECC added to the write data to perform an error detection correction of data read from the flash memory.

14. The memory system according to claim 13, wherein the ECC circuit generates the ECC to be added to the write data and the dummy data that are to be written into the flash memory.

15. The memory system according to claim 8, wherein the memory is a data-writing buffer into the flash memory, for the write data to be written into the flash memory.

16. The memory system according to claim 8, wherein the memory is a DRAM.

17. The memory system according to claim 8, further comprising:

a micro processing unit that controls an operation of the memory system;

an interface unit that performs an interface process of performing a data transfer to an external device; and

a controller that performs an interface process between the memory controller and the memory and that is used by the memory controller to access the memory.

18. The memory system according to claim 17, wherein the micro processing unit, the interface unit, and the controller are mounted on an ASIC chip, and the memory is arranged outside the ASIC chip.

19. A method of controlling access to a flash memory in which a memory controller controls access to a flash memory in which data is written in a page size unit according to data-write request information, the method comprising:

the memory controller acquiring write data to be written into the flash memory according to the data-write request information;

the memory controller adding dummy data to the write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to the data-write request information does not match the page size unit and adjusting the size of the write data to the page size unit; and

the memory controller outputting the write data by referring the instruction information.