VIRTUAL MEMORY INTERFACE

• US 20090216964A1
• Filed: 02/27/2008
• Published: 08/27/2009
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Palladino, Michael, Kleveland, Bendik, Gyllenhammer, Carl
• Granted Patent: US 8,219,778 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.

Claims

1. Apparatus, comprising:

a memory comprising data storage locations addressable by physical addresses; and

a direct memory access (DMA) controller providing a virtual memory interface to the memory and operable to apply a virtual address in a flat memory linear addressing space as an index into a sequence of the physical addresses that is ordered in accordance with a group of buffers.

2. The apparatus of claim 1, wherein

in response to receipt of the virtual address, the DMA controller maps the virtual address to a target one of the physical addresses having a sequence position offset from a reference position in the sequence by an amount corresponding to an amount by which the virtual address is offset from a reference position in the flat memory linear addressing space.

3. The apparatus of claim 2, wherein

in mapping the virtual address to the respective physical address, the DMA controller increments a buffer address list index to an index value of a target one of the buffers encompassing the target physical address and incrementing a buffer offset by an amount corresponding to an offset between a starting physical address of the target buffer and the target physical address.

4. The apparatus of claim 1, wherein

in response to receipt of the virtual address in association with a data transfer request, the DMA controller uses the virtual address to identify a target one of the physical addresses in a target one of the buffers and performs data transfer operations with respect to the target storage location at the identified physical address.

5. The apparatus of claim 1, wherein the group of buffers is referenced by a list of buffer reference elements each of which comprises (i) a respective buffer pointer corresponding to a respective one of the physical addresses and (ii) a respective buffer size.

6. The apparatus of claim 5, further comprising a second DMA controller operable to build the list of buffer reference elements after data is written to the buffers.

7. The apparatus of claim 5, wherein

in response to a request to write data to the memory, the DMA controller builds the list of buffer reference elements in accordance with a group of buffers scattered in the memory.

8. The apparatus of claim 1, further comprising a wireless transceiver operable to transmit and receive packets of data, wherein the received packet data is stored in buffers scattered in the memory and each of the received packets is associated with a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer;

wherein, for each of the received packets, the DMA controller is operable to apply a virtual address in a respective flat memory linear addressing space as an index into a sequence of the physical addresses that is ordered in accordance with the respective buffer reference element list.

9. The apparatus of claim 8, wherein the memory, the DMA controller, and the wireless transceiver are implemented on a single semiconductor chip.

10. Apparatus, comprising:

a memory comprising data storage locations addressable by physical addresses;

a wireless transceiver operable to transmit and receive packets of data;

logic operable to store packet data in buffers scattered in the memory and to associate with each of the stored packets a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer; and

a virtual memory interface operable to provide random access to individual ones of the data storage locations based on respective orderings of ones of the physical addresses into respective sequences in accordance with respective ones of the lists of buffer reference elements and on a respective indexing of each the ordered physical address sequences with consecutive virtual addresses in a flat memory linear addressing space.

11. The apparatus of claim 10, wherein

in response to receipt of a respective one of the virtual addresses in association with a data transfer request with respect to a particular packet, the virtual memory interface is operable to resolve the received virtual address to a target one of the physical addresses based on the respective indexing and to perform data transfer operations with respect to the data storage location at the target physical address.

12. The apparatus of claim 10, wherein the virtual memory interface is operable to provide a bus master device with random access to individual ones of the data storage locations.

13. The apparatus of claim 10, wherein the memory, the wireless transceiver, the logic, and the virtual memory interface are implemented on a single semiconductor chip.

14. A method, comprising:

fetching a list of buffer reference elements each of which comprises (i) a respective buffer pointer corresponding to a respective one of physical addresses of data storage locations in a memory and (ii) a respective buffer size;

ordering ones of the physical addresses into a sequence in accordance with the list of buffer reference elements;

applying a virtual address in a flat memory linear addressing space as an index into the sequence of the physical addresses to identify a target one of the data storage locations; and

performing data transfer operations with respect to the target data storage locations.

15. The method of claim 14, further comprising

in response to receipt of the virtual address, selecting as the target physical address the physical address having a sequence position offset from a reference position in the sequence by an amount corresponding to an amount by which the virtual address is offset from a reference position in the flat memory linear addressing space.

16. The method of claim 15, wherein the selecting comprises

incrementing a buffer address list index to an index value of the buffer reference element that comprises a buffer pointer to a target buffer encompassing the target physical address, and

incrementing a buffer offset by an amount corresponding to an offset between the physical address of the target buffer and the target physical address.

17. The method of claim 14, wherein the accessing comprises

in response to receipt of the virtual address in association with a data transfer request, using the virtual address to identify a target one of the physical addresses in a target buffer scattered in the memory and performing data transfer operations with respect to the data storage location at the target physical address.

18. The method of claim 14, further comprising building the list of buffer reference elements in accordance with a group of buffers scattered in the memory.

19. A method, comprising:

wirelessly transmitting and receiving packets of data;

storing packet data in buffers scattered in a memory that comprises data storage locations addressable by physical addresses;

associating with each of the stored packets a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer; and

providing random access to individual ones of the data storage locations based on respective orderings of ones of the physical addresses into respective sequences in accordance with respective ones of the lists of buffer reference elements and on a respective indexing of each the ordered physical address sequences with consecutive virtual addresses in a flat memory linear addressing space.

20. The method of claim 19, wherein in response to receipt of a respective one of the virtual addresses in association with a data transfer request with respect to a particular packet,

resolving the received virtual address to a target one of the physical addresses based on the respective indexing, and

performing data transfer operations with respect to the data storage location at the target physical address.