Structure For Detecting Clock Gating Opportunities In A Pipelined Electronic Circuit Design
First Claim
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- a pipeline electronic processor device including a plurality of pipeline stages, the plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on a simulation of the pipeline electronic processor device that specifies the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation.
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Abstract
A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
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Citations
18 Claims
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1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a pipeline electronic processor device including a plurality of pipeline stages, the plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on a simulation of the pipeline electronic processor device that specifies the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a pipeline electronic processor device, wherein said HDL design structure comprises:
a first element processed to generate a functional computer-simulated representation of the pipeline electronic processor device including a plurality of pipeline stages, the plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on a simulation of the pipeline electronic processor device that specifies the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method in a computer-aided design system for generating a functional design model of a pipeline electronic processor device, the method comprising:
generating a functional computer-simulated representation of the pipeline electronic processor device including a plurality of pipeline stages, the plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on a simulation of the pipeline electronic processor device that specifies the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation. - View Dependent Claims (14, 15, 16, 17, 18)
Specification