METHOD OF MAKING AN INTEGRATED CIRCUIT USING PRE-DEFINED INTERCONNECT WIRING

• US 20090217228A1
• Filed: 02/26/2008
• Published: 08/27/2009
• Est. Priority Date: 02/26/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Melzner, Hanno
• Granted Patent: US 7,962,878 B2
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Claims

1. A method of configuring an integrated circuit, the method comprising:

configuring a plurality of cells to form a cell library, wherein configuring each cell includes;

defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals; and

defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal;

arranging selected cells from the cell library to form a desired layout of an integrated circuit; and

routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

2. The method of claim 1, including removing up to all portions non-selected candidate wires.

3. The method of claim 2, including removing only end portions of one or more non-selected candidate wires and employing a remaining portion the one or more non-selected candidate wires as fill structures.

4. The method of claim 1, wherein defining candidate wires includes defining one or more candidate vias and required metal extensions for each terminal.

5. The method of claim 4, wherein candidate vias are positioned based on wiring tracks of upper metal layers.

6. The method of claim 1, wherein defining candidate wires includes defining one or more candidate terminal wires from each terminal to a border connection point along at least one border of the cell.

7. The method of claim 6, wherein defining candidate terminal wires includes defining candidate border terminal wires from each border terminal to a border connection point along at least one border of the cell.

8. The method of claim 6, wherein defining candidate terminal wires includes defining candidate inner terminal wires from each inner terminal to a border connection point along at least one border of the cell.

9. The method of claim 6, wherein ends of candidate terminal wires proximate to a border connection point have a width based on a set of relaxed design rules.

10. The method of claim 6, wherein border connection points along horizontal cell borders are arranged on a grid.

11. The method of claim 6, wherein border connection points along vertical cell borders are arranged on a grid.

12. The method of claim 1, wherein routing intercell wiring includes routing interconnect wires in the at least one layer of a filler cell along a pre-defined grid.

13. The method of claim 11, wherein the pre-defined grid and intercell wiring in the filler cell is based on a set of relaxed design rules.

14. The method of claim 1, wherein the at least one terminal comprises each terminal of the cell.

15. A semiconductor cell for use in a cell library employed for forming an integrated circuit, the cell comprising:

a plurality of active areas in a substrate, including transistor gates;

a plurality of intracell wiring in at least one metal layer positioned above the substrate, the intracell wiring connecting to the active areas in the substrate and forming one or more terminals; and

one or more candidate wires for each terminal to use as pre-defined intercell wiring within borders of the cell in the at least one metal layer for connection to each terminal.

16. The semiconductor cell of claim 15, wherein the candidate wires include one or more candidate vias and associated metal extensions for each terminal.

17. The semiconductor cell of claim 15, wherein the candidate wires include one or more candidate terminal wires from each terminal to a border connection point along at least one border of the cell.

18. The semiconductor cell of claim 17, wherein the candidate terminal wires include candidate border terminal wires and candidate inner terminal wires.

19. The semiconductor cell of claim 17, wherein border connection points along horizontal cell borders of the cell are arranged on a grid.

20. The semiconductor cell of claim 17, wherein border connection points along vertical cell borders of the cell are arranged on a grid.

21. A method of configuring an integrated circuit, the method comprising:

configuring a plurality of cells to form a cell library, wherein configuring each cell includes;

defining a plurality of active areas in a substrate, including transistor gates;

defining intracell wiring in at least one layer positioned above the substrate, the intracell wiring connecting to the active areas and forming one or more terminals; and

defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal;

arranging selected cells from the cell library to form a desired layout of an integrated circuit;

routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells; and

removing up to all portions of non-selected candidate wires.

22. The method of claim 21, wherein defining one or more candidate wires is done by hand.

23. The method of claim 21, wherein routing intercell wiring and removing non-selected candidate wires is performed using an automated routing tool.

24. The method of claim 21, including:

identifying intracell wiring as a first data type; and

identifying candidate wires as a second data type.

25. A computer-readable medium having computer-executable instructions for configuring an integrated circuit, comprising:

configuring a plurality of cells to form a cell library, wherein configuring each cell includes;

defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals; and

defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal;

arranging selected cells from the cell library to form a desired layout of an integrated circuit;

routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells; and

moving up to all portions non-selected candidate wires.