LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES
First Claim
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1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design tool, comprising:
- converting synchronous logic gates represented by the netlist to asynchronous logic gates;
replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates;
inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to normalize path lengths through the asynchronous pipelines thereby achieving a level of performance; and
removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic with substantially no impact on the level of performance.
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Abstract
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
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Citations
15 Claims
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1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design tool, comprising:
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converting synchronous logic gates represented by the netlist to asynchronous logic gates; replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates; inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to normalize path lengths through the asynchronous pipelines thereby achieving a level of performance; and removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic with substantially no impact on the level of performance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification