LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES

• US 20090217232A1
• Filed: 05/04/2009
• Published: 08/27/2009
• Est. Priority Date: 11/22/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Fulcrum Microsystems, Inc. (Intel Corporation)
• Inventors: Lines, Andrew, Davies, Michael, Beerel, Peter
• Granted Patent: US 8,051,396 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed

Abstract

Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

Claims

1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design tool, comprising:

converting synchronous logic gates represented by the netlist to asynchronous logic gates;

replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates;

inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to normalize path lengths through the asynchronous pipelines thereby achieving a level of performance; and

removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic with substantially no impact on the level of performance.

2. The method of claim 1 wherein removal of the selected buffers is accomplished using one of an integer linear programming (ILP) technique, a mixed-integer linear programming (MILP) technique, and a linear programming (LP) technique.

3. The method of claim 1 further comprising generating the netlist using the synchronous CAD tool.

4. The method of claim 3 wherein the netlist originates from a register transfer language (RTL) specification.

5. The method of claim 1 further comprising performing logic synthesis on the netlist to generate the synchronous logic gates.

6. The method of claim 1 further comprising selecting portions of synchronous logic represented by the netlist for conversion to the asynchronous logic.

7. The method of claim 1 wherein converting the synchronous logic gates to the asynchronous logic gates comprises replacing single-rail logic gates with dual-rail equivalents.

8. The method of claim 7 further comprising deriving the single-rail logic gates from a library of dual-rail logic gates.

9. The method of claim 8 wherein deriving the single-rail logic gates from the library of dual-rail logic gates comprises mapping dual-rail timing arcs to synchronous equivalents.

10. The method of claim 1 wherein the asynchronous logic gates comprise domino logic gates, and the asynchronous logic comprises multi-level domino logic.

11. At least one computer-readable medium having data structures stored therein resulting from the method of claim 1 and representative of the circuit.

12. The at least one computer-readable medium of claim 11 wherein the data structures comprise a simulatable representation of the circuit.

13. The at least one computer-readable medium of claim 12 wherein the simulatable representation comprises a netlist.

14. The at least one computer-readable medium of claim 11 wherein the data structures comprise a code description of the circuit.

15. The at least one computer-readable medium of claim 14 wherein the code description corresponds to a hardware description language.