SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES

• US 20090218603A1
• Filed: 05/08/2009
• Published: 09/03/2009
• Est. Priority Date: 06/21/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Robert S. Chau, Suman Datta, Uday Shah
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Datta, Suman
• Granted Patent: US 8,071,983 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/30617 Anisotropic liquid etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Claims

1. An integrated circuit comprising:

a first nonplanar transistor having a first semiconductor body comprising V-notched sidewalls, wherein charge migration in the first semiconductor body is along a first direction; and

a second nonplanar transistor having a second semiconductor body comprising inwardly tapered sidewalls, wherein charge migration in the second semiconductor body is along a second direction, and wherein the second direction is not parallel to the first direction.

2. The integrated circuit of claim 1, wherein the first direction is approximately 45 degrees with respect to the second direction.

3. The integrated circuit of claim 1, wherein the first nonplanar transistor is an n type field effect transistor, wherein the first semiconductor body is formed from a single crystalline silicon film, and wherein the first direction is parallel to a <

100>

plane of the single crystalline silicon film.

4. The integrated circuit of claim 1, wherein the second nonplanar transistor is a p type field effect transistor, wherein the second semiconductor body is a single crystalline silicon film, and wherein the second direction is parallel to a <

110>

plane.

5. The integrated circuit of claim 1, wherein the second nonplanar transistor is a p type field effect transistor, wherein the second semiconductor body is formed from a single crystalline silicon film, wherein the second direction is parallel to a <

110>

plane of the silicon film, wherein the first nonplanar transistor is an n type field effect transistor, wherein the first semiconductor body is a single crystalline silicon film, and wherein the first direction is parallel to a <

100>

plane.

6. The integrated circuit of claim 1, wherein the inwardly tapered sidewalls each taper inward from the top of the second semiconductor body at an angle of approximately 62.5 degrees.

7. The integrated circuit of claim 6, wherein each sidewall is flat from the top of the second semiconductor body to the bottom of the second semiconductor body.

8. The integrated circuit of claim 1, wherein the V-notched sidewalls each notch inward from the sides of the first semiconductor body at an angle of approximately 55 degrees.

9. The integrated circuit of claim 8, wherein each sidewall is flat from the top of the first semiconductor body to the center of the V-notch, and is flat from the center of the V-notch to the bottom of the first semiconductor body.

10. The integrated circuit of claim 1, wherein charge migration in the second semiconductor body is along a direction perpendicular to the inwardly tapered sidewalls.

11. The integrated circuit of claim 1, wherein charge migration in the first semiconductor body is along a direction perpendicular to the V-notched sidewalls.

12. A nonplanar transistor, comprising:

a semiconductor body comprising inwardly tapered sidewalls, wherein charge migration in the semiconductor body is along a direction perpendicular to the sidewalls; and

a gate electrode disposed over the semiconductor body and orthogonal to the direction of charge migration.

13. The nonplanar transistor of claim 12, wherein the inwardly tapered sidewalls each taper inward from the top of the semiconductor body at an angle of approximately 62.5 degrees.

14. The nonplanar transistor of claim 12, wherein each sidewall is flat from the top of the semiconductor body to the bottom of the semiconductor body.

15. The nonplanar transistor of claim 12, wherein the nonplanar transistor is a p type field effect transistor, wherein the semiconductor body is formed from a single crystalline silicon film, and wherein the direction perpendicular to the sidewalls is parallel to a <

110>

plane of the single crystalline silicon film.

16. A nonplanar transistor, comprising:

a semiconductor body comprising V-notched sidewalls, wherein charge migration in the semiconductor body is along a direction perpendicular to the V-notched sidewalls; and

a gate electrode disposed over the semiconductor body and orthogonal to the direction of charge migration.

17. The nonplanar transistor of claim 16, wherein the V-notched sidewalls each notch inward from the sides of the semiconductor body at an angle of approximately 55 degrees.

18. The nonplanar transistor of claim 16, wherein each sidewall is flat from the top of the semiconductor body to the center of the V-notch, and is flat from the center of the V-notch to the bottom of the semiconductor body.

19. The nonplanar transistor of claim 16, wherein the nonplanar transistor is an n type field effect transistor, wherein the semiconductor body is formed from a single crystalline silicon film, and wherein the direction perpendicular to the sidewalls is parallel to a <

100>

plane of the single crystalline silicon film.