SUPERJUNCTION POWER SEMICONDUCTOR DEVICE

• US 20090218617A1
• Filed: 02/17/2009
• Published: 09/03/2009
• Est. Priority Date: 01/24/2007
• Status: Abandoned Application

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Inventors: Kinzer, Daniel M.
• Application Number:
  US12/372,639
• Publication Number:
  US 20090218617A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device.

Claims

1. A power semiconductor device comprising:

a semiconductor substrate of one conductivity;

an epitaxial semiconductor body of another conductivity on a surface of said substrate;

a gate trench in said epitaxial semiconductor body;

a drift region of said one conductivity extending from at least the bottom of said trench to said substrate and extending along only a portion of the sidewalls of said gate trench, said drift region of said one conductivity and said epitaxial semiconductor body being in charge balance;

a source region of said one conductivity formed in said epitaxial semiconductor body adjacent said gate trench and spaced from said drift region of said one conductivity by an invertible channel region adjacent said trench;

a source contact in ohmic contact with at least said source region;

a drain contact in ohmic contact with said substrate.

2. The power semiconductor device of claim 1, wherein said drift region of said one conductivity extends into said substrate.

3. The power semiconductor device of claim 1, wherein said drift region includes a high resistivity region adjacent said substrate and a low resistivity region adjacent said gate trench.

4. The power semiconductor body of claim 1, further comprising an oxide body disposed inside said trench, said oxide body including a gate oxide portion adjacent at least said invertible channel and a thick portion adjacent the drift region;

and a gate electrode inside said trench and adjacent said oxide body.

5. The power semiconductor body of claim 1, further comprising a high conductivity region of said second conductivity formed in said epitaxial silicon body and making ohmic contact with said source contact.

6. The power semiconductor body of claim 4, wherein said gate electrode is comprised of polysilicon.

7. The power semiconductor body of claim 6, wherein said polysilicon is N type.

8. The power semiconductor body of claim 1, wherein said first conductivity is N type and said second conductivity is P type.