SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME

• US 20090218618A1
• Filed: 03/03/2008
• Published: 09/03/2009
• Est. Priority Date: 03/03/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Roesch, Maximilian, Blank, Oliver, Hiller, Uli, Rieger, Walter
• Granted Patent: US 7,833,862 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material forming a field electrode in a lower portion of the trench;

forming a cover comprising a second material above the field electrode, the first isolating material being selectively etchable to the second material;

removing the sidewall isolation in an upper portion of the trench;

forming a gate dielectric on the sidewall in the upper portion of the trench; and

forming a gate electrode in the upper portion of the trench.

2. The method of claim 1, wherein the second material is an isolating material.

3. The method of claim 2, wherein the second material is silicon nitride.

4. The method of claim 1, wherein the second material is a conductive or semi conductive material.

5. The method of claim 4, wherein the second material is polysilicon.

6. The method of claim 4, wherein the cover comprises an isolating layer which is formed on top of the field electrode before the second material is deposited.

7. The method of claim 1, wherein the process of forming the cover comprises the process of conformal depositing the second material.

8. The method of claim 1, wherein the process of forming the field electrode comprises the process of conformal depositing the material of the field electrode.

9. The method of claim 1, wherein the process of removing the sidewall isolation comprises process of etching the first isolating material selectively to the second material.

10. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material forming a field electrode in a lower portion of the trench;

forming a cover comprising a second material above the field electrode, the first isolating material being selectively etchable to the second material;

removing the sidewall isolation in an upper portion of the trench;

forming a gate dielectric on the sidewall in the upper portion of the trench; and

forming a gate electrode in the upper portion of the trench, including defining the trench along its lateral extend to comprise a first portion where the cover above the field electrode is formed and a second portion where a conductive connection to the field electrode is formed.

11. The method of claim 10, wherein the first portion of the trench has a first width and the second portion of the trench has second width, the second width being larger than the first width.

12. The method of claim 10, wherein the process of forming the cover comprises the process of selectively covering the second portion of the trench with a mask material and removing the material of the field electrode from an upper portion of the trench.

13. A semiconductor device, comprising:

a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material;

a field electrode formed in lower portion of the trench;

a cover comprising a second material above the field electrode, the first isolating material being selectively etchable to the second material;

a gate dielectric on the sidewall in an upper portion of the trench; and

a gate electrode in the upper portion of the trench.

14. The semiconductor device of claim 13, wherein the second material is an isolating material.

15. The semiconductor device of claim 14, wherein the second material is a silicon nitride.

16. The semiconductor device of claim 13, wherein the second material is a conductive or semi conductive material.

17. The semiconductor device of claim 16, wherein the second material is polysilicon.

18. The semiconductor device of claim 16, wherein the cover comprises an isolating layer which is formed on top of the field electrode before the second material is deposited.

19. The semiconductor device of claim 13, wherein the cover overlaps with the gate electrode in the vertical direction.

20. The semiconductor device of claim 19, wherein the overlap is larger than 10% of the height of the electrode in the vertical direction.

21. The semiconductor device of claim 19, wherein the overlap is larger than 50% of the height of the electrode in the vertical direction.

22. The semiconductor device of claim 19, wherein the overlap is larger than 90% of the height of the electrode in the vertical direction.

23. A semiconductor device, comprising:

a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material;

a field electrode formed in lower portion of the trench;

a cover comprising a second material above the field electrode, the first isolating material being selectively etchable to the second material;

a gate dielectric on the sidewall in an upper portion of the trench; and

a gate electrode in the upper portion of the trench, and

wherein the trench along its lateral extend comprises a first portion where the cover above the field electrode is formed and a second portion where a conductive connection to the field electrode is formed.

24. The semiconductor device of claim 23, wherein the first portion of the trench has a first width and the second portion of the trench has second width, the second width being larger than the first width.

25. A semiconductor device, comprising:

a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material;

a field electrode formed in lower portion of the trench;

means for providing a cover comprising a second material above the field electrode, the first isolating material being selectively etchable to the second material;

a gate dielectric on the sidewall in an upper portion of the trench; and

a gate electrode in the upper portion of the trench.