Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method

• US 20090218619A1
• Filed: 03/02/2008
• Published: 09/03/2009
• Est. Priority Date: 03/02/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Hebert, Francois, Bobde, Madhur
• Granted Patent: US 8,878,292 B2
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

Claims

1. An accumulation mode field effect transistor (AccuFET) comprising:

trenched gates each having a stick-up gate segment extended above a top surface of said semiconductor substrate surrounded by sidewall spacers; and

slots opened aligned with said sidewall spacers substantially parallel to said trenched gates.

2. The accumulation mode field effect transistor of claim 1 wherein:

said stick-up gate segment further having a cap composed of an insulation material surrounded by said sidewall spacers.

3. The accumulation mode field effect transistor of claim 2 further comprising:

a layer of barrier metal covering a top surface of said cap and over said sidewall spacers extending above a top surface of said slots.

4. The accumulation mode field effect transistor of claim 1 wherein:

said slots filled with a conductive material for functioning as additional gate electrodes.

5. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

said slots filled with a conductive material same as said gate segment for providing a depletion layer extends toward said trenched gates whereby a drift region between said slots and said trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

6. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

sidewalls of said slots are doped with dopant ions opposite polarity to that of the drain.

7. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

sidewalls of said slots are doped with body dopant ions opposite polarity to that of the drain and said slots are filled with a planarized doped polysilicon.

8. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

sidewalls of said slots are doped with dopant ions opposite polarity to that of the drain and said slots are filled with a dielectric material therefore said doped sidewalls around the slots are floating.

9. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

sidewalls of said slots are doped with dopant ions opposite polarity to that of the drain and said slots are open slots with a top of said open slots and said sidewalls covered by a barrier metal layer.

10. The accumulation mode field effect transistor semiconductor power device of claim 9 wherein:

said barrier metal layer composed of a Schottky metal layer.

11. The accumulation mode field effect transistor semiconductor power device of claim 9 wherein:

said barrier metal layer composed of an ohmic metal layer.

12. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

sidewalls of said slots are doped with dopant ions opposite polarity to that of the drain and said slots are filled with an insulation material whereby said sidewalls doped with said dopant ions having a floating voltage for reducing a leakage current.

13. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

said slots are filled with an insulation material for providing a fixed termination to maintain a threshold voltage of a depletion region extended from said trench gates.

14. The accumulation mode field effect transistor semiconductor power device of claim 1 wherein:

said sidewall spacers and said sidewalls of said slots are covered with a Schottky barrier metal with said slots to function as Schottky slots.

15. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

accumulation mode field effect transistor (AccuFET) cells configured as stripe cells.

16. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

accumulation mode field effect transistor (AccuFET) cells configured as closed cells.

17. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

accumulation mode field effect transistor (AccuFET) cells supported on an epitaxial layer near a top surface of said semiconductor substrate wherein said epitaxial layer having a thickness greater than a highly doped source contact diffusion region and shallower than said trenched gates of said AccuFET cells.

18. An accumulation mode field effect transistor (AccuFET) disposed on an epitaxial layer overlaying a semiconductor substrate comprising:

a trench gate filled in a first trench extending into the epitaxial layer to a first depth;

a source region surrounding a top portion of the trench gate disposed onto a top of the epitaxial layer to a second depth shallower than the first depth; and

a second trench next to the source region away from the first trench extend into the epitaxial layer to a third depth deeper than the second depth, whereas said second trench is lined with a Schottky barrier metal layer to function as Schottky diodes for minimizing a forward conduction loss.

19. The accumulation mode field effect transistor of claim 18 further comprising:

a Shannon implant below said Schottky barrier metal layer for adjusting the barrier height of Schottky diode.

20. An accumulation mode field effect transistor (AccuFET) disposed on an epitaxial layer overlaying a semiconductor substrate comprising:

a trench gate filled in a first trench extending into the epitaxial layer to a first depth;

A source region surrounding a top portion of the trench gate disposed onto a top of the epitaxial layer to a second depth; and

a second trench next to the source region away from the first trench extend into the epitaxial layer to a third depth, whereas said second trench is filled with conductive material same as the trenched gate.

21. The accumulation mode field effect transistor of claim 20 further comprising:

a doped region of opposite polarity to the epitaxial layer type disposed along a sidewall and bottom of the second trench.

22. The accumulation mode field effect transistor of claim 20 whereas:

said epitaxial layer further comprising a first epitaxial layer overlaying a second epitaxial layer, said first epitaxial layer having a thickness less than the depth of the first trench and a doping concentration less than that of second epitaxial layer.

23. An accumulation mode field effect transistor (AccuFET) disposed on an epitaxial layer overlaying a semiconductor substrate comprising:

a trench gate filled in a first trench extending into the epitaxial layer to a first depth;

A source region surrounding a top portion of the trench gate disposed onto a top of the epitaxial layer to a second depth; and

a second trench next to the source region away from the first trench extend into the epitaxial layer to a third depth, whereas said second trench is filled with dielectric material.

24. The accumulation mode field effect transistor of claim 23 further comprising:

a doping layer of dopant opposite to the epitaxial layer type disposed along a sidewall and bottom of the second trench.

25. A method for manufacturing a semiconductor power device disposed in a semiconductor substrate comprising:

forming trenched gates with a stick-up gate segment extended above a top surface of said semiconductor substrate surrounded by sidewall spacers; and

applying a self-aligned etching process to open slots aligned with said sidewall spacers substantially parallel to said trenched gates.