FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT

• US 20090218627A1
• Filed: 02/28/2008
• Published: 09/03/2009
• Est. Priority Date: 02/28/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong
• Application Number:
  US12/039,063
• Publication Number:
  US 20090218627A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence

Abstract

A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via preferably comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate electrode at the center of which may be located a non-annular and non-spacer shaped second contact via. The annular gate electrode as well as the annular contact via and the non-annular contact via may be formed sequentially in a self-aligned fashion while using a single sacrificial mandrel layer.

Claims

1. A semiconductor structure comprising:

a gate electrode located over a channel region within a semiconductor substrate that separates a pair of source/drain regions within the semiconductor substrate; and

a spacer shaped contact via located upon one of the source/drain regions and electrically isolated from the gate electrode.

2. The semiconductor structure of claim 1 wherein the spacer shaped contact via has a tip that points in the direction of the gate electrode.

3. The semiconductor structure of claim 1 wherein the gate electrode comprises an annular gate electrode.

4. The semiconductor structure of claim 3 wherein the spacer shaped contact via comprises an annular spacer shaped contact via that surrounds the annular gate electrode.

5. The semiconductor structure of claim 1 wherein the gate electrode also has a spacer shape.

6. The semiconductor structure of claim 5 wherein the spacer shaped gate electrode and the spacer shaped contact via point in the same direction.

7. The semiconductor structure of claim 6 further comprising a second contact via upon another of the source/drain regions, where the second contact via does not have a spacer shape.

8. The semiconductor structure of claim 7 wherein the second contact via is surrounded by the annular gate electrode.

9. A semiconductor structure comprising:

an annular spacer shaped gate electrode located at least in part over a channel region within a semiconductor substrate that separates a pair of source/drain regions within the semiconductor substrate; and

an annular spacer shaped contact via located at least in part upon one of the source/drain regions, the annular spacer shaped contact via surrounding and being electrically isolated from the gate electrode.

10. The semiconductor structure of claim 9 wherein the annular gate electrode is located completely over the channel region.

11. The semiconductor structure of claim 9 wherein the annular gate electrode is in part not located over the channel region.

12. The semiconductor structure of claim 9 further comprising a non annular contact via located upon another of the source/drain regions.

13. The semiconductor structure of claim 9 wherein the annular spacer shaped gate electrode and the annular spacer shaped contact via point in the same direction.

14. A method for fabricating a semiconductor structure comprising:

forming a gate electrode annularly surrounding a sacrificial layer located over a semiconductor substrate;

removing the sacrificial layer from over the semiconductor to leave remaining the annular gate electrode;

forming a first source/drain region within the semiconductor substrate outside of the annular gate electrode and a second source/drain region inside the annular gate electrode; and

forming an annular contact via contacting the first source/drain region and surrounding the annular gate electrode.

15. The method of claim 14 wherein the forming the annular gate electrode forms an annular spacer shaped gate electrode.

16. The method of claim 14 wherein the forming the annular contact via forms an annular spacer shaped contact via.

17. The method of claim 14 wherein the forming the annular contact via simultaneously forms a second contact via upon the second source/drain region.

18. The method of claim 17 wherein the second contact via is not annular.

19. The method of claim 14 wherein the forming the annular gate electrode comprises an anisotropic etch method to provide a spacer shaped annular gate electrode

20. The method of claim 14 wherein the forming the annular contact via comprises an anisotropic etch method to provide a spacer shaped annular contact via.