Barrier for Copper Integration in the FEOL

• US 20090218692A1
• Filed: 02/29/2008
• Published: 09/03/2009
• Est. Priority Date: 02/29/2008
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hampp, Roland
• Application Number:
  US12/040,441
• Publication Number:
  US 20090218692A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Copper integration in the FEOL stage is disclosed for a preliminary semiconductor device by forming a recess in a substrate of the device, the recess having a bottom surface and sidewall surfaces, depositing a barrier layer having about a 100% step coverage on the sidewall surfaces and the bottom surface, and depositing copper into the recess over the barrier layer to form a contact providing electrical connection to the preliminary semiconductor device.

Claims

1. A method of making a semiconductor device, said method comprising:

forming an active device is a semiconductor body;

forming an insulating layer over the active device;

forming a recess in the insulating layer, said recess having a bottom surface and sidewall surfaces, the bottom surface overlying a portion of the active device;

forming a barrier layer having about a 100% step coverage over the sidewall surfaces and said bottom surface; and

filling said recess with copper that overlies said barrier layer to form a contact, the contact in direct electrical connection with the active device.

2. The method of claim 1, wherein forming said barrier layer comprises depositing said barrier layer using an atomic layer deposition (ALD).

3. The method of claim 1, wherein said barrier layer comprises tantalum.

4. The method of claim 3, wherein said barrier layer comprises tantalum nitride.

5. The method of claim 1, wherein the recess exposes a surface of the active device.

6. The method of claim 5, wherein the recess exposes a semiconductor surface.

7. The method of claim 6, wherein the barrier layer is formed in direct contact with the semiconductor surface.

8. The method of claim 5, wherein the recess exposes a silicide surface.

9. The method of claim 8, wherein the barrier layer is formed in direct contact with the silicide surface.

10. A method of making a semiconductor device, said method comprising:

forming an active device is a semiconductor body;

forming an insulating layer over the active device;

forming a recess in the insulating layer, said recess having a bottom surface and sidewall surfaces, the bottom surface overlying a portion of the active device;

forming a barrier layer over the sidewall surfaces and said bottom surface, the barrier being formed using an atomic layer deposition (ALD) process; and

filling said recess with copper that overlies said barrier layer to form a contact, the contact in direct electrical connection with the active device.

11. The method of claim 10, wherein said barrier layer comprises tantalum.

12. The method of claim 11, wherein said barrier layer comprises tantalum nitride.

13. The method of claim 10, wherein the recess exposes a surface of the active device.

14. The method of claim 13, wherein the recess exposes a semiconductor surface.

15. The method of claim 14, wherein the barrier layer is formed in direct contact with the semiconductor surface.

16. The method of claim 13, wherein the recess exposes a silicide surface.

17. The method of claim 16, wherein the barrier layer is formed in direct contact with the silicide surface.

18. The method of claim 10, wherein filling said recess with copper comprises completely filling said recess.

19. A semiconductor device comprising:

a semiconductor component disposed at a surface of a semiconductor body;

an insulating layer overlying the semiconductor body;

a copper contact directly electrically connected to said semiconductor component, wherein the copper contact extending through the insulating layer; and

a barrier layer located between the copper contact and said insulating layer, wherein said barrier layer is formed to create about a 100% step coverage to shield said insulating layer and the semiconductor body from copper diffusing from said copper contact.

20. The semiconductor device of claim 19, wherein barrier layer comprises a barrier layer formed by an atomic layer deposition (ALD) process.

21. The semiconductor device of claim 19, wherein said barrier layer comprises tantalum.

22. The semiconductor device of claim 19, wherein said barrier layer comprises tantalum nitride.