Three dimensional structure memory

• US 20090218700A1
• Filed: 03/17/2009
• Published: 09/03/2009
• Est. Priority Date: 04/04/1997
• Status: Active Grant

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J.
• Granted Patent: US 8,928,119 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit 1 comprising:

a plurality of thinned substantially flexible integrated circuits having topside and bottom-side surfaces, wherein each of said integrated circuits are stacked in relation to one another; and

interconnections electrically connecting the plurality of thinned substantially flexible integrated circuits, wherein the interconnections are formed only on said surfaces.

2. The apparatus of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.

3. The apparatus of claim 1, wherein the plurality of thinned substantially flexible integrated circuits comprises one of a single crystal semiconductor material and a polycrystalline semiconductor material.

4. The apparatus of claim 1, wherein the plurality of thinned substantially flexible integrated circuits comprise one of a logic integrated circuit and a memory integrated circuit.

5. The apparatus of claim 4, wherein the logic integrated circuit is a microprocessor integrated circuit.

6. The apparatus of claim 1, wherein the plurality of thinned substantially flexible integrated circuits comprise logic integrated circuits.

7. The apparatus of claim 1, wherein at least one of the interconnections electrically interconnecting the plurality of thinned substantially flexible integrated circuits are vertical interconnections.

8. The apparatus of claim 1, wherein at least one of the plurality of thinned substantially flexible integrated circuits is formed with a low stress dielectric.

9. The apparatus of claim 8, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.