Three dimensional structure memory

• US 20090219743A1
• Filed: 03/17/2009
• Published: 09/03/2009
• Est. Priority Date: 04/04/1997
• Status: Abandoned Application

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J.
• Application Number:
  US12/405,237
• Publication Number:
  US 20090219743A1
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit comprising:

a logic layer including means for initiating a memory access;

at least one memory layer; and

an array of vertical interconnects between the logic layer and the at least one memory layer for routing data vertically between the logic layer and selected storage locations within the at least one memory layer;

wherein during a single memory access cycle, a plurality of bytes of data are routed from the selected storage locations to the logic layer.

2. The apparatus of claim 1, wherein said array is an array of vertical interconnections interior to the stacked integrated circuit.

3. The apparatus of claim 1, wherein the logic layer comprises means for receiving a virtual address and translating the virtual address to a real address.

4. The apparatus of claim 1, wherein the logic layer comprises means for receiving an indirect address and translating the indirect address to one of a real address and a virtual address.

5. The apparatus of claim 1, wherein the at least one memory layer comprises at least one content-addressable memory circuit, wherein the logic layer receives a content word and produces as an output signal an address of the content word within the at least one memory circuit.

6. The apparatus of claim 1, wherein the logic layer comprises means for performing at least one of audio encoding and audio decoding of data that is one of read from and written to the memory layer.

7. The apparatus of claim 1, wherein the logic layer comprises means for performing at least one of video encoding and video decoding of data that is one of read from and written to the at least one memory layer.

8. The apparatus of claim 1, wherein the logic layer comprises means for performing recognition of data that is one of read from and written to the at least one memory layer.

9. The apparatus of claim 8, wherein recognition processing is voice recognition processing.

10. The apparatus of claim 8, wherein recognition processing is hand writing recognition processing.

11. The apparatus of claim 1, wherein the logic layer comprises means for performing power management functions.

12. The apparatus of claim 1, wherein the logic layer comprises means for performing graphics acceleration functions.

13. The apparatus of claim 1, wherein the logic layer comprises means for performing database processing functions.

14. The apparatus of claim 1, wherein the logic layer comprises a microprocessor.

15. The apparatus of claim 1, wherein the logic layer is fabricated using one process technology, and the at least one memory layer is fabricated using a different process technology.

16. The apparatus of claim 15, wherein the different process technology is selected from a group consisting of:

DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

17. The apparatus of claim 1, wherein the at least one memory layer is formed from one of single crystal semiconductor material and polycrystalline semiconductor material.

28. The apparatus of claim 1, wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

29. The apparatus of claim 1, wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

30. The apparatus of claim 1, wherein at least one of the logic and the memory layers comprises a microprocessor.

31. The apparatus of claim 1, wherein the logic layer performs testing of the at least one memory layer.

32. The apparatus of claim 1, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

33. The apparatus of claim 1, wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

34. The apparatus of claim 1, wherein a plurality of interior vertical interconnections traverse at least one of the layers.

35. The apparatus of claim 1, wherein continuous vertical interconnections connect circuitry of the layers.

36. The apparatus of claim 1, wherein information processing is performed on data routed between circuitry on two or more of the layers.

37. The apparatus of claim 1, wherein at least one of the layers has reconfiguration circuitry.

38. The apparatus of claim 1, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

39. The apparatus of claim 1, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

40. The apparatus of claim 1, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

41. The apparatus of claim 40, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

42. The apparatus of claim 40, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

43. The apparatus of claim 40, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

44. The apparatus of claim 40, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

45. The apparatus of claim 40, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

46. The apparatus of claim 40, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

129. The apparatus of claim 1, wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.

130. The apparatus of claim 1, wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

18. A stacked integrated circuit memory comprising:

circuit layers having at least one logic layer and at least one memory layer; and

a plurality of connections interior to the stacked integrated circuit memory for vertically routing data within the stacked integrated circuit memory during a memory access.

19. The apparatus of claim 18, wherein the at least one logic layer is a microprocessor layer.

20. The apparatus of claim 18, wherein the at least one logic layer is a memory controller layer.

21. The apparatus of claim 18, wherein the at least one logic layer performs programmable gate line address assignment.

22. The apparatus of claim 21, wherein the programmable gate-line address assignment provides for the use of at least one redundant gate line.

23. The apparatus of claim 18, wherein the at least one logic layer can perform self test of at least one of the memory layers.

24. The apparatus of claim 18, wherein at least one of the at least one logic layer and the at least one memory layer is made with polysilicon circuits.

25. The apparatus of claim 18, wherein the at least one logic layer is fabricated using a process technology, and the at least one memory layer is fabricated using a different process technology.

26. The apparatus of claim 25, wherein the at least one memory layer is made with a process technology from a group consisting of:

DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

27. The apparatus of claim 18, wherein the at least one logic layer includes logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

47. The apparatus of claim 18, wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

48. The apparatus of claim 18, wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM/Ferroelectric and Giant Magneto Resistance.

49. The apparatus of claim 18, wherein at least one of the logic and the memory layers comprises a microprocessor.

50. The apparatus of claim 18, wherein the logic layer performs testing of the at least one memory layer.

51. The apparatus of claim 18, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

52. The apparatus of claim 18, wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

53. The apparatus of claim 18, wherein a plurality of interior vertical interconnections traverse at least one of the layers.

54. The apparatus of claim 18, wherein continuous vertical interconnections connect circuitry of the layers.

55. The apparatus of claim 18, wherein information processing is performed on data routed between circuitry on two or more of the layers.

56. The apparatus of claim 18, wherein at least one of the layers has reconfiguration circuitry.

57. The apparatus of claim 18, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

58. The apparatus of claim 18, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

59. The apparatus of claim 18, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines! said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering! in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

60. The apparatus of claim 59, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

61. The apparatus of claim 59, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

62. The apparatus of claim 59, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

63. The apparatus of claim 59, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

64. The apparatus of claim 59, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

65. The apparatus of claim 59, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

131. The apparatus of claim 18, wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.

132. The apparatus of claim 18, wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

66. An information processing integrated circuit comprising:

stacked integrated circuit layers having a logic layer and a memory layer; and

logic on the logic layer for initiating a memory access;

wherein vertical interconnections route data of the memory access interior to the stacked integrated circuit layers between the logic layer and at least one memory location on the a memory layer.

67. The apparatus of claim 66, wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

68. The apparatus of claim 66, wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

69. The apparatus of claim 66, wherein at least one of the logic and the memory layers comprises a microprocessor.

70. The apparatus of claim 66, wherein the logic layer performs testing of the at least one memory layer.

71. The apparatus of claim 66, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

72. The apparatus of claim 66, wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

73. The apparatus of claim 66, wherein a plurality of interior vertical interconnections traverse at least one of the layers.

74. The apparatus of claim 66, wherein continuous vertical interconnections connect circuitry of the layers.

75. The apparatus of claim 66, wherein information processing is performed on data routed between circuitry on two or more of the layers.

76. The apparatus of claim 66, wherein at least one of the layers has reconfiguration circuitry.

77. The apparatus of claim 66, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

78. The apparatus of claim 66, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

79. The apparatus of claim 66, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

80. The apparatus of claim 79, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

81. The apparatus of claim 79, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

82. The apparatus of claim 79, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

83. The apparatus of claim 79, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

84. The apparatus of claim 79, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

85. The apparatus of claim 79, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

126. The apparatus of claim 66, wherein the logic layer is fabricated using one process technology, and the memory layer is fabricated using a different process technology.

133. The apparatus of claim 66, wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.

134. The apparatus of claim 66, wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

86. An information processing integrated circuit comprising:

stacked integrated circuit layers having a logic layer and a memory layer; and

a plurality of vertical interconnections interior to the stacked integrated circuit layers for the transfer of data between the logic layer and the memory circuit layer of said information processing integrated circuit.

87. The apparatus of claim 86, wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

88. The apparatus of claim 86, wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

89. The apparatus of claim 86, wherein at least one of the logic and the memory layers comprises a microprocessor.

90. The apparatus of claim 86, wherein the logic layer performs testing of the at least one memory layer.

91. The apparatus of claim 86, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

92. The apparatus of claim 86, wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

93. The apparatus of claim 86, wherein a plurality of interior vertical interconnections traverse at least one of the layers.

94. The apparatus of claim 86, wherein continuous vertical interconnections connect circuitry of the layers.

95. The apparatus of claim 86, wherein information processing is performed on data routed between circuitry on two or more of the layers.

96. The apparatus of claim 86, wherein at least one of the layers has reconfiguration circuitry.

97. The apparatus of claim 86, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

98. The apparatus of claim 86, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

99. The apparatus of claim 86, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

100. The apparatus of claim 99, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

101. The apparatus of claim 99, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

102. The apparatus of claim 99, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

103. The apparatus of claim 99, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

104. The apparatus of claim 99, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

105. The apparatus of claim 99, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

127. The apparatus of claim 86, wherein the logic layer is fabricated using one process technology, and the memory layer is fabricated using a different process technology.

135. The apparatus of claim 86, wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.

136. The apparatus of claim 86, wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

106. An integrated circuit comprising:

stacked integrated circuit layers having a logic layer and a memory layer; and

vertical interconnections interior to the integrated circuit with at least one of the vertical interconnections formed through the memory layer of said integrated circuit.

107. The apparatus of claim 106, wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

108. The apparatus of claim 106, wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

109. The apparatus of claim 106, wherein at least one of the logic and the memory layers comprises a microprocessor.

110. The apparatus of claim 106, wherein the logic layer performs testing of the at least one memory layer.

111. The apparatus of claim 106, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

112. The apparatus of claim 106, wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

113. The apparatus of claim 106, wherein a plurality of interior vertical interconnections traverse at least one of the layers.

114. The apparatus of claim 106, wherein continuous vertical interconnections connect circuitry of the layers.

115. The apparatus of claim 106, wherein information processing is performed on data routed between circuitry on two or more of the layers.

116. The apparatus of claim 106, wherein at least one of the layers has reconfiguration circuitry.

117. The apparatus of claim 106, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

118. The apparatus of claim 106, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

119. The apparatus of claim 106, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

120. The apparatus of claim 119, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

121. The apparatus of claim 119, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

122. The apparatus of claim 119, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

123. The apparatus of claim 119, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

124. The apparatus of claim 119, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

125. The apparatus of claim 119, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

128. The apparatus of claim 106, wherein the logic layer is fabricated using one process technology, and the memory layer is fabricated using a different process technology.

137. The apparatus of claim 106, wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.

138. The apparatus of claim 106, wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.