Three dimensional structure memory

• US 20090219744A1
• Filed: 03/17/2009
• Published: 09/03/2009
• Est. Priority Date: 04/04/1997
• Status: Active Grant

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Granted Patent: US 8,318,538 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of information processing using a plurality of stacked integrated circuits of equal size and aligned by at least one edge, each of the integrated circuits having major surfaces and bonds formed over a full extent of at least one major surface of each integrated circuit, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring information through vertical transmission paths between two or more of the plurality of integrated circuits a portion of at least one of the paths formed from a portion of one of the bonds; and

ii. storing and retrieving information over the vertical transmission paths, wherein at least one of error detection and error correction is performed on the information by at least one of the integrated circuits.

2. A method of information processing using a plurality of stacked integrated circuits of equal size and aligned by at least one edge, each of the integrated circuits having major surfaces and bonds formed over a full extent of at least one major surface of each integrated circuit, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring information through at least one of the bonds of at least one major surface;

storing and retrieving the information from at least one of the integrated circuits; and

ii. performing at least one of error detection and error correction on the information.

3. A method of information processing using a plurality of stacked integrated circuits of equal size and aligned by at least one edge, each of the integrated circuits having major surfaces and bonds formed over a full extent of at least one major surface of each integrated circuit, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. configuring at least one integrated circuit to prevent at least a portion of said integrated circuit from use; and

ii. transferring information through at least one bond of at least one major surface of at least one integrated circuit.

4. A method of information processing using a plurality of stacked integrated circuits of equal size and aligned by at least one edge, each of the integrated circuits having major surfaces and bonds formed over a full extent of at least one major surface of each integrated circuit, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring address information between at least two of the integrated circuits; and

ii. transferring information to at least one integrated circuit corresponding to the address information.

5. A method of information processing using a plurality of stacked integrated circuits and an array of vertical interconnection paths that pass through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transfering information through the vertical transmission paths; and

,

ii. the information of at least one transfer comprising at least a majority of a row of a memory circuit array on one of the other integrated circuits.

6. A method of information processing using a plurality of stacked integrated circuits and an array of vertical interconnection paths that pass through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring information through the vertical transmission paths;

ii. the information of at least one transfer comprising at least a majority of a row of a memory circuit array on one of the other integrated circuits; and

iii. at least one of the integrated circuits has been electronically configured to prevent the operation of a portion of said integrated circuit.

7. A method of information processing using a plurality of stacked integrated circuits and an array of vertical interconnection paths that pass through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring information through the vertical transmission paths;

ii. the information of at least one transfer comprising at least a majority of a row of a memory circuit array on one of the other integrated circuits; and

iii. performing at least one of error detection and correction on the information.

8. A method of information processing using a plurality of stacked integrated circuits and an array of vertical interconnection paths that pass through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible, the method comprising:

i. transferring address information between at least two of the integrated circuits; and

ii. transferring information to at least one integrated circuit corresponding to the address information.

9. Electronic circuitry comprising a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits and at least one of the integrated circuits is thinned and flexible, wherein information is stored on a first one of the integrated circuits and passes through at least one of the transmission paths for processing on a second one of the integrated circuits.

10. Electronic circuitry comprising a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible and at least one of the integrated circuits has been configured to prevent the operation of a portion of said integrated circuit, wherein information is stored on a first one of the integrated circuits and passes through at least one of the transmission paths for processing on a second one of the integrated circuits.

11. Electronic circuitry comprising a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits, at least one of the integrated circuits is thinned and flexible and at least one of the integrated circuits is able to be configured to prevent the operation of a portion of said integrated circuit, wherein information is stored on a first one of the integrated circuits and passes through at least one of the transmission paths for processing on a second one of the integrated circuits.

12. Electronic circuitry comprising a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits and at least one of the integrated circuits is thinned and flexible, wherein information is stored on a first one of the integrated circuits and passes through at least one of the transmission paths for processing on a second one of the integrated circuits and at least one of error detection and correction is performed on the information.

13. Electronic circuitry for information processing using a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits, wherein signals from a first one of the integrated circuits passes through at least one of the transmission paths for enabling the operation of all or a portion of the circuitry of a second one of the integrated circuits.

14. Electronic circuitry for information processing using a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits, wherein address signals from a first one of the integrated circuits passes through at least one of the transmission paths for accessing memory cells on a second one of the integrated circuits.

15. Electronic circuitry for information processing using a stack of integrated circuits of equal size and held in an unmovable relation to one another with transmission paths passing through at least one of the integrated circuits, wherein signals from a first one of the integrated circuits passes through at least one of the transmission paths for disabling the operation of all or a portion of the circuitry of a second one of the integrated circuits.

16. Electronic circuitry for information processing using a stack of integrated circuits of equal size and held in an unmovable relation to one another with a plurality of transmission paths passing through at least one of the integrated circuits, wherein multiple address signals from a first one of the integrated circuits passes through the plurality transmission paths for simultaneously and independently accessing memory cells on at least a second one of the integrated circuits.