×

Three dimensional structure memory

  • US 20090219744A1
  • Filed: 03/17/2009
  • Published: 09/03/2009
  • Est. Priority Date: 04/04/1997
  • Status: Active Grant
First Claim
Patent Images

1. A method of information processing using a plurality of stacked integrated circuits of equal size and aligned by at least one edge, each of the integrated circuits having major surfaces and bonds formed over a full extent of at least one major surface of each integrated circuit, at least one of the integrated circuits is thinned and flexible, the method comprising:

  • i. transferring information through vertical transmission paths between two or more of the plurality of integrated circuits a portion of at least one of the paths formed from a portion of one of the bonds; and

    ii. storing and retrieving information over the vertical transmission paths, wherein at least one of error detection and error correction is performed on the information by at least one of the integrated circuits.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×