LOW POWER DIGITAL DESIGN FOR DEEP SUBMICRON TECHNOLOGY

• US 20090222055A1
• Filed: 02/27/2009
• Published: 09/03/2009
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Maile, Keith R., Huelskamp, Paul, Gifford, Douglas J., Reedstrom, Scott A.
• Granted Patent: US 8,060,204 B2
• Time in Patent Office: Days
• US Class Current: 607/27
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/3931 Protecting, e.g. back-up systems

Abstract

An apparatus comprises an implantable medical device that includes a storage circuit. The storage circuit includes a first stage circuit configured to receive an input signal and to invert and store information about a data bit received in the input signal, a second stage circuit coupled to the output of the first stage circuit to invert and store information about a data bit received from the first stage circuit, and an error circuit coupled to the output of the first stage circuit and an output of the second stage circuit. The error circuit generates an error indication when the storage circuit outputs match while the first stage circuit and the second stage circuit are in an inactive state.

Claims

1. An apparatus comprising:

an implantable medical device including a storage circuit comprising;

a first stage circuit configured to receive an input signal and to invert and store a data bit received in the input signal;

a second stage circuit coupled to an output of the first stage circuit to invert and store a data bit received from the first stage circuit; and

an error circuit coupled to the output of the first stage circuit and an output of the second stage circuit, wherein the error circuit is configured to generate an error indication when the storage circuit outputs provide matching data bits while the first stage circuit and the second stage circuit are in an inactive state.

2. The apparatus of claim 1, wherein the storage circuit includes:

a clock circuit configured to receive a global clock signal and an off signal, and to provide a local clock signal to the first stage and second stage circuits, wherein the local clock signal is disabled when the off signal is received;

wherein the first stage circuit includes a first latch circuit having cross coupled logic gates configured to invert and store a data bit received in the input signal;

wherein the second stage circuit includes a second latch circuit having cross coupled logic gates configured to invert and store a data bit received from the first latch circuit; and

wherein the error circuit is configured to generate an error indication when the outputs provide matching data bits while the off signal is active.

3. The apparatus of claim 2, wherein the second stage circuit is configured to store data on an opposite level of the global clock signal from the first stage circuit.

4. The apparatus of claim 1, wherein the implantable medical device includes a plurality of storage circuits associated with respective error circuits, and wherein the error circuits are serially connected to form an error indication chain.

5. The apparatus of claim 1, wherein the storage circuit includes a first transistor having a voltage threshold that is lower than a voltage threshold of a second transistor of the storage circuit.

6. The apparatus of claim 5, wherein the first transistor is included in a signal path that is more time sensitive than a signal path including the second transistor.

7. The apparatus of claim 5, wherein the implantable medical device includes:

a logic gate circuit including a stack of three series connected transistors, wherein the three series connected transistors includes a first transistor having a voltage threshold that is lower than a voltage threshold of at least one of the other two transistors in the stack; and

wherein a gate of the first transistor is configured to receive an off signal to place the first transistor, the first stage storage circuit, and the second stage storage circuit in an inactive state.

8. The apparatus of claim 1, wherein the implantable medical device includes a redundancy circuit comprising:

first, second, and third logic circuits, wherein the second and third logic circuits are redundant instantiations of the first logic circuit; and

a voting circuit configured to determine an output of the redundancy circuit according to a majority of outputs of the first, second, and third logic circuits.

9. The apparatus of claim 1, wherein the storage circuit includes a first transistor that is wider than a second transistor of the storage circuit.

10. The apparatus of claim 1, wherein the implantable medical device comprises a cardiac function management device.

11. The apparatus of claim 1, wherein the implantable medical device comprises at least one of a neural stimulation device, a drug delivery device, or a diagnostic device.

12. A method comprising:

storing, in a storage circuit of an implantable medical device, information to represent both an inverted version of a data bit and a non-inverted version of the data bit;

disabling clocking of the storage circuit; and

generating an error indication when the stored information to represent the inverted and non-inverted versions of the data bit match while the clocking is disabled.

13. The method of claim 12, including:

identifying a time sensitive signal path in the implantable device, wherein the time sensitive path includes the storage circuit; and

providing a first transistor having a voltage threshold that is lower than a voltage threshold of a second transistor, wherein the first transistor is included in the time critical signal path of the storage circuit, and wherein the second transistor is not included in the time critical signal path of the storage circuit.

14. The method of claim 12, including:

providing a logic gate circuit that includes three series connected transistors, and wherein the three series connected transistors includes a first transistor having a voltage threshold lower than the voltage threshold of at least one of the other two transistors in the stack; and

disabling the first transistor when disabling the clocking of the storage circuit.

15. The method of claim 12, including:

generating first, second, and third logic outputs, and wherein the second and third logic outputs are generated using logic that is redundant to logic used to generate the first and second logic outputs; and

voting using the first, second, and third logic outputs to determine a majority output.

16. The method of claim 12, including:

providing a clock signal to the storage circuit; and

storing information to represent the inverted version of the data bit on an opposite level of the clock signal than the information to represent the non-inverted version of data bit.

17. The method of claim 12, including:

providing a plurality of the storage circuits in association with respective error circuits;

serially connecting the error circuits of the storage circuits into an error chain; and

propagating an error indication to an output of the error chain when an error occurs in any of the storage circuits during disabling of the clocking of the storage circuits.

18. The method of claim 12, including rewriting a register that includes a plurality of the storage circuits when an error indication is generated.

19. The method of claim 12, comprising using the error indication to detect a disruption to operation of a cardiac function management device.

20. The method of claim 12, comprising using the error indication to detect a disruption to operation of at least one of a neural stimulation device, a drug delivery device, or a diagnostic device.